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Update nrf-hal to v0.12.1

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Use the `psel_bits()` method to reduce #[cfg] clutter
This commit is contained in:
Timo Kröger 2021-03-05 09:23:44 +01:00
parent bd3deb785a
commit 28b2365ef3
6 changed files with 25 additions and 88 deletions
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2
embassy-nrf-examples/Cargo.toml
View file

@ -28,5 +28,5 @@ cortex-m = { version = "0.7.1", features = ["inline-asm"] }
cortex-m-rt = "0.6.13" cortex-m-rt = "0.6.13"
embedded-hal = { version = "0.2.4" } embedded-hal = { version = "0.2.4" }
panic-probe = "0.1.0" panic-probe = "0.1.0"
nrf52840-hal = { version = "0.12.0" } nrf52840-hal = { version = "0.12.1" }
futures = { version = "0.3.8", default-features = false, features = ["async-await"] } futures = { version = "0.3.8", default-features = false, features = ["async-await"] }

10
embassy-nrf/Cargo.toml
View file

@ -35,8 +35,8 @@ nrf52832-pac = { version = "0.9.0", optional = true }
nrf52833-pac = { version = "0.9.0", optional = true } nrf52833-pac = { version = "0.9.0", optional = true }
nrf52840-pac = { version = "0.9.0", optional = true } nrf52840-pac = { version = "0.9.0", optional = true }
nrf52810-hal = { version = "0.12.0", optional = true } nrf52810-hal = { version = "0.12.1", optional = true }
#nrf52811-hal = { version = "0.12.0", optional = true } # doesn't exist yet #nrf52811-hal = { version = "0.12.1", optional = true } # doesn't exist yet
nrf52832-hal = { version = "0.12.0", optional = true } nrf52832-hal = { version = "0.12.1", optional = true }
nrf52833-hal = { version = "0.12.0", optional = true } nrf52833-hal = { version = "0.12.1", optional = true }
nrf52840-hal = { version = "0.12.0", optional = true } nrf52840-hal = { version = "0.12.1", optional = true }

26
embassy-nrf/src/buffered_uarte.rs
View file

@ -15,7 +15,6 @@ use embassy::io::{AsyncBufRead, AsyncWrite, Result};
use embassy::util::WakerRegistration; use embassy::util::WakerRegistration;
use embedded_hal::digital::v2::OutputPin; use embedded_hal::digital::v2::OutputPin;
use crate::hal::gpio::Port as GpioPort;
use crate::hal::ppi::ConfigurablePpi; use crate::hal::ppi::ConfigurablePpi;
use crate::interrupt::{self, Interrupt}; use crate::interrupt::{self, Interrupt};
use crate::pac; use crate::pac;
@ -72,14 +71,6 @@ pub struct BufferedUarte<
inner: PeripheralMutex<State<'a, U, T, P1, P2>>, inner: PeripheralMutex<State<'a, U, T, P1, P2>>,
} }
#[cfg(any(feature = "52833", feature = "52840"))]
fn port_bit(port: GpioPort) -> bool {
match port {
GpioPort::Port0 => false,
GpioPort::Port1 => true,
}
}
impl<'a, U: Instance, T: TimerInstance, P1: ConfigurablePpi, P2: ConfigurablePpi> impl<'a, U: Instance, T: TimerInstance, P1: ConfigurablePpi, P2: ConfigurablePpi>
BufferedUarte<'a, U, T, P1, P2> BufferedUarte<'a, U, T, P1, P2>
{ {
@ -97,25 +88,19 @@ impl<'a, U: Instance, T: TimerInstance, P1: ConfigurablePpi, P2: ConfigurablePpi
) -> Self { ) -> Self {
// Select pins // Select pins
uarte.psel.rxd.write(|w| { uarte.psel.rxd.write(|w| {
let w = unsafe { w.pin().bits(pins.rxd.pin()) }; unsafe { w.bits(pins.rxd.psel_bits()) };
#[cfg(any(feature = "52833", feature = "52840"))]
let w = w.port().bit(port_bit(pins.rxd.port()));
w.connect().connected() w.connect().connected()
}); });
pins.txd.set_high().unwrap(); pins.txd.set_high().unwrap();
uarte.psel.txd.write(|w| { uarte.psel.txd.write(|w| {
let w = unsafe { w.pin().bits(pins.txd.pin()) }; unsafe { w.bits(pins.txd.psel_bits()) };
#[cfg(any(feature = "52833", feature = "52840"))]
let w = w.port().bit(port_bit(pins.txd.port()));
w.connect().connected() w.connect().connected()
}); });
// Optional pins // Optional pins
uarte.psel.cts.write(|w| { uarte.psel.cts.write(|w| {
if let Some(ref pin) = pins.cts { if let Some(ref pin) = pins.cts {
let w = unsafe { w.pin().bits(pin.pin()) }; unsafe { w.bits(pin.psel_bits()) };
#[cfg(any(feature = "52833", feature = "52840"))]
let w = w.port().bit(port_bit(pin.port()));
w.connect().connected() w.connect().connected()
} else { } else {
w.connect().disconnected() w.connect().disconnected()
@ -124,15 +109,14 @@ impl<'a, U: Instance, T: TimerInstance, P1: ConfigurablePpi, P2: ConfigurablePpi
uarte.psel.rts.write(|w| { uarte.psel.rts.write(|w| {
if let Some(ref pin) = pins.rts { if let Some(ref pin) = pins.rts {
let w = unsafe { w.pin().bits(pin.pin()) }; unsafe { w.bits(pin.psel_bits()) };
#[cfg(any(feature = "52833", feature = "52840"))]
let w = w.port().bit(port_bit(pin.port()));
w.connect().connected() w.connect().connected()
} else { } else {
w.connect().disconnected() w.connect().disconnected()
} }
}); });
// Enable UARTE instance // Enable UARTE instance
uarte.enable.write(|w| w.enable().enabled()); uarte.enable.write(|w| w.enable().enabled());

27
embassy-nrf/src/qspi.rs
View file

@ -3,7 +3,7 @@ use core::pin::Pin;
use core::task::Poll; use core::task::Poll;
use crate::fmt::{assert, assert_eq, *}; use crate::fmt::{assert, assert_eq, *};
use crate::hal::gpio::{Output, Pin as GpioPin, Port as GpioPort, PushPull}; use crate::hal::gpio::{Output, Pin as GpioPin, PushPull};
use crate::interrupt::{self}; use crate::interrupt::{self};
use crate::pac::QSPI; use crate::pac::QSPI;
@ -59,43 +59,31 @@ pub struct Qspi {
inner: PeripheralMutex<State>, inner: PeripheralMutex<State>,
} }
fn port_bit(port: GpioPort) -> bool {
match port {
GpioPort::Port0 => false,
GpioPort::Port1 => true,
}
}
impl Qspi { impl Qspi {
pub fn new(qspi: QSPI, irq: interrupt::QSPI, config: Config) -> Self { pub fn new(qspi: QSPI, irq: interrupt::QSPI, config: Config) -> Self {
qspi.psel.sck.write(|w| { qspi.psel.sck.write(|w| {
let pin = &config.pins.sck; let pin = &config.pins.sck;
let w = unsafe { w.pin().bits(pin.pin()) }; unsafe { w.bits(pin.psel_bits()) };
let w = w.port().bit(port_bit(pin.port()));
w.connect().connected() w.connect().connected()
}); });
qspi.psel.csn.write(|w| { qspi.psel.csn.write(|w| {
let pin = &config.pins.csn; let pin = &config.pins.csn;
let w = unsafe { w.pin().bits(pin.pin()) }; unsafe { w.bits(pin.psel_bits()) };
let w = w.port().bit(port_bit(pin.port()));
w.connect().connected() w.connect().connected()
}); });
qspi.psel.io0.write(|w| { qspi.psel.io0.write(|w| {
let pin = &config.pins.io0; let pin = &config.pins.io0;
let w = unsafe { w.pin().bits(pin.pin()) }; unsafe { w.bits(pin.psel_bits()) };
let w = w.port().bit(port_bit(pin.port()));
w.connect().connected() w.connect().connected()
}); });
qspi.psel.io1.write(|w| { qspi.psel.io1.write(|w| {
let pin = &config.pins.io1; let pin = &config.pins.io1;
let w = unsafe { w.pin().bits(pin.pin()) }; unsafe { w.bits(pin.psel_bits()) };
let w = w.port().bit(port_bit(pin.port()));
w.connect().connected() w.connect().connected()
}); });
qspi.psel.io2.write(|w| { qspi.psel.io2.write(|w| {
if let Some(ref pin) = config.pins.io2 { if let Some(ref pin) = config.pins.io2 {
let w = unsafe { w.pin().bits(pin.pin()) }; unsafe { w.bits(pin.psel_bits()) };
let w = w.port().bit(port_bit(pin.port()));
w.connect().connected() w.connect().connected()
} else { } else {
w.connect().disconnected() w.connect().disconnected()
@ -103,8 +91,7 @@ impl Qspi {
}); });
qspi.psel.io3.write(|w| { qspi.psel.io3.write(|w| {
if let Some(ref pin) = config.pins.io3 { if let Some(ref pin) = config.pins.io3 {
let w = unsafe { w.pin().bits(pin.pin()) }; unsafe { w.bits(pin.psel_bits()) };
let w = w.port().bit(port_bit(pin.port()));
w.connect().connected() w.connect().connected()
} else { } else {
w.connect().disconnected() w.connect().disconnected()

21
embassy-nrf/src/spim.rs
View file

@ -5,7 +5,6 @@ use core::task::Poll;
use embassy::util::WakerRegistration; use embassy::util::WakerRegistration;
use futures::future::poll_fn; use futures::future::poll_fn;
use crate::hal::gpio::Port as GpioPort;
use crate::interrupt::{self, Interrupt}; use crate::interrupt::{self, Interrupt};
use crate::util::peripheral::{PeripheralMutex, PeripheralState}; use crate::util::peripheral::{PeripheralMutex, PeripheralState};
use crate::{pac, slice_in_ram_or}; use crate::{pac, slice_in_ram_or};
@ -33,14 +32,6 @@ pub struct Spim<T: Instance> {
inner: PeripheralMutex<State<T>>, inner: PeripheralMutex<State<T>>,
} }
#[cfg(any(feature = "52833", feature = "52840"))]
fn port_bit(port: GpioPort) -> bool {
match port {
GpioPort::Port0 => false,
GpioPort::Port1 => true,
}
}
pub struct Config { pub struct Config {
pub pins: Pins, pub pins: Pins,
pub frequency: Frequency, pub frequency: Frequency,
@ -54,26 +45,20 @@ impl<T: Instance> Spim<T> {
// Select pins. // Select pins.
r.psel.sck.write(|w| { r.psel.sck.write(|w| {
let w = unsafe { w.pin().bits(config.pins.sck.pin()) }; unsafe { w.bits(config.pins.sck.psel_bits()) };
#[cfg(any(feature = "52833", feature = "52840"))]
let w = w.port().bit(port_bit(config.pins.sck.port()));
w.connect().connected() w.connect().connected()
}); });
match config.pins.mosi { match config.pins.mosi {
Some(mosi) => r.psel.mosi.write(|w| { Some(mosi) => r.psel.mosi.write(|w| {
let w = unsafe { w.pin().bits(mosi.pin()) }; unsafe { w.bits(mosi.psel_bits()) };
#[cfg(any(feature = "52833", feature = "52840"))]
let w = w.port().bit(port_bit(mosi.port()));
w.connect().connected() w.connect().connected()
}), }),
None => r.psel.mosi.write(|w| w.connect().disconnected()), None => r.psel.mosi.write(|w| w.connect().disconnected()),
} }
match config.pins.miso { match config.pins.miso {
Some(miso) => r.psel.miso.write(|w| { Some(miso) => r.psel.miso.write(|w| {
let w = unsafe { w.pin().bits(miso.pin()) }; unsafe { w.bits(miso.psel_bits()) };
#[cfg(any(feature = "52833", feature = "52840"))]
let w = w.port().bit(port_bit(miso.port()));
w.connect().connected() w.connect().connected()
}), }),
None => r.psel.miso.write(|w| w.connect().disconnected()), None => r.psel.miso.write(|w| w.connect().disconnected()),

27
embassy-nrf/src/uarte.rs
View file

@ -13,8 +13,6 @@ use embassy::interrupt::InterruptExt;
use embassy::util::Signal; use embassy::util::Signal;
use crate::fmt::{assert, *}; use crate::fmt::{assert, *};
#[cfg(any(feature = "52833", feature = "52840"))]
use crate::hal::gpio::Port as GpioPort;
use crate::hal::pac; use crate::hal::pac;
use crate::hal::prelude::*; use crate::hal::prelude::*;
use crate::hal::target_constants::EASY_DMA_SIZE; use crate::hal::target_constants::EASY_DMA_SIZE;
@ -40,15 +38,6 @@ pub struct State {
rx_done: Signal<u32>, rx_done: Signal<u32>,
} }
// TODO: Remove when https://github.com/nrf-rs/nrf-hal/pull/276 has landed
#[cfg(any(feature = "52833", feature = "52840"))]
fn port_bit(port: GpioPort) -> bool {
match port {
GpioPort::Port0 => false,
GpioPort::Port1 => true,
}
}
impl<T> Uarte<T> impl<T> Uarte<T>
where where
T: Instance, T: Instance,
@ -72,26 +61,20 @@ where
assert!(uarte.enable.read().enable().is_disabled()); assert!(uarte.enable.read().enable().is_disabled());
uarte.psel.rxd.write(|w| { uarte.psel.rxd.write(|w| {
let w = unsafe { w.pin().bits(pins.rxd.pin()) }; unsafe { w.bits(pins.rxd.psel_bits()) };
#[cfg(any(feature = "52833", feature = "52840"))]
let w = w.port().bit(port_bit(pins.rxd.port()));
w.connect().connected() w.connect().connected()
}); });
pins.txd.set_high().unwrap(); pins.txd.set_high().unwrap();
uarte.psel.txd.write(|w| { uarte.psel.txd.write(|w| {
let w = unsafe { w.pin().bits(pins.txd.pin()) }; unsafe { w.bits(pins.txd.psel_bits()) };
#[cfg(any(feature = "52833", feature = "52840"))]
let w = w.port().bit(port_bit(pins.txd.port()));
w.connect().connected() w.connect().connected()
}); });
// Optional pins // Optional pins
uarte.psel.cts.write(|w| { uarte.psel.cts.write(|w| {
if let Some(ref pin) = pins.cts { if let Some(ref pin) = pins.cts {
let w = unsafe { w.pin().bits(pin.pin()) }; unsafe { w.bits(pin.psel_bits()) };
#[cfg(any(feature = "52833", feature = "52840"))]
let w = w.port().bit(port_bit(pin.port()));
w.connect().connected() w.connect().connected()
} else { } else {
w.connect().disconnected() w.connect().disconnected()
@ -100,9 +83,7 @@ where
uarte.psel.rts.write(|w| { uarte.psel.rts.write(|w| {
if let Some(ref pin) = pins.rts { if let Some(ref pin) = pins.rts {
let w = unsafe { w.pin().bits(pin.pin()) }; unsafe { w.bits(pin.psel_bits()) };
#[cfg(any(feature = "52833", feature = "52840"))]
let w = w.port().bit(port_bit(pin.port()));
w.connect().connected() w.connect().connected()
} else { } else {
w.connect().disconnected() w.connect().disconnected()