Dario Nieuwenhuis
GitHub
commit
2e625138ff
4 changed files with 511 additions and 22 deletions
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@ -1,22 +1,106 @@
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use core::future::poll_fn;
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use core::marker::PhantomData;
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use core::ops::{Deref, DerefMut};
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use core::task::Poll;
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pub use bxcan;
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use bxcan::{Data, ExtendedId, Frame, Id, StandardId};
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use embassy_hal_common::{into_ref, PeripheralRef};
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use futures::FutureExt;
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use crate::gpio::sealed::AFType;
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use crate::interrupt::typelevel::Interrupt;
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use crate::pac::can::vals::{Lec, RirIde};
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use crate::rcc::RccPeripheral;
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use crate::{peripherals, Peripheral};
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use crate::time::Hertz;
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use crate::{interrupt, peripherals, Peripheral};
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/// Interrupt handler.
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pub struct TxInterruptHandler<T: Instance> {
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_phantom: PhantomData<T>,
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}
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impl<T: Instance> interrupt::typelevel::Handler<T::TXInterrupt> for TxInterruptHandler<T> {
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unsafe fn on_interrupt() {
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T::regs().tsr().write(|v| {
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v.set_rqcp(0, true);
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v.set_rqcp(1, true);
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v.set_rqcp(2, true);
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});
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T::state().tx_waker.wake();
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}
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}
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pub struct Rx0InterruptHandler<T: Instance> {
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_phantom: PhantomData<T>,
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}
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impl<T: Instance> interrupt::typelevel::Handler<T::RX0Interrupt> for Rx0InterruptHandler<T> {
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unsafe fn on_interrupt() {
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// info!("rx0 irq");
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Can::<T>::receive_fifo(RxFifo::Fifo0);
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}
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}
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pub struct Rx1InterruptHandler<T: Instance> {
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_phantom: PhantomData<T>,
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}
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impl<T: Instance> interrupt::typelevel::Handler<T::RX1Interrupt> for Rx1InterruptHandler<T> {
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unsafe fn on_interrupt() {
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// info!("rx1 irq");
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Can::<T>::receive_fifo(RxFifo::Fifo1);
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}
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}
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pub struct SceInterruptHandler<T: Instance> {
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_phantom: PhantomData<T>,
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}
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impl<T: Instance> interrupt::typelevel::Handler<T::SCEInterrupt> for SceInterruptHandler<T> {
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unsafe fn on_interrupt() {
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// info!("sce irq");
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let msr = T::regs().msr();
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let msr_val = msr.read();
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if msr_val.erri() {
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msr.modify(|v| v.set_erri(true));
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T::state().err_waker.wake();
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}
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}
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}
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pub struct Can<'d, T: Instance> {
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can: bxcan::Can<BxcanInstance<'d, T>>,
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}
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#[derive(Debug)]
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pub enum BusError {
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Stuff,
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Form,
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Acknowledge,
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BitRecessive,
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BitDominant,
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Crc,
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Software,
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BusOff,
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BusPassive,
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BusWarning,
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}
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impl<'d, T: Instance> Can<'d, T> {
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/// Creates a new Bxcan instance, blocking for 11 recessive bits to sync with the CAN bus.
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/// Creates a new Bxcan instance, keeping the peripheral in sleep mode.
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/// You must call [Can::enable_non_blocking] to use the peripheral.
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pub fn new(
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peri: impl Peripheral<P = T> + 'd,
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rx: impl Peripheral<P = impl RxPin<T>> + 'd,
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tx: impl Peripheral<P = impl TxPin<T>> + 'd,
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_irqs: impl interrupt::typelevel::Binding<T::TXInterrupt, TxInterruptHandler<T>>
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+ interrupt::typelevel::Binding<T::RX0Interrupt, Rx0InterruptHandler<T>>
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+ interrupt::typelevel::Binding<T::RX1Interrupt, Rx1InterruptHandler<T>>
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+ interrupt::typelevel::Binding<T::SCEInterrupt, SceInterruptHandler<T>>
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+ 'd,
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) -> Self {
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into_ref!(peri, rx, tx);
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@ -26,30 +110,242 @@ impl<'d, T: Instance> Can<'d, T> {
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T::enable();
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T::reset();
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Self {
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can: bxcan::Can::builder(BxcanInstance(peri)).enable(),
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}
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}
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{
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use crate::pac::can::vals::{Errie, Fmpie, Tmeie};
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/// Creates a new Bxcan instance, keeping the peripheral in sleep mode.
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/// You must call [Can::enable_non_blocking] to use the peripheral.
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pub fn new_disabled(
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peri: impl Peripheral<P = T> + 'd,
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rx: impl Peripheral<P = impl RxPin<T>> + 'd,
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tx: impl Peripheral<P = impl TxPin<T>> + 'd,
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) -> Self {
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into_ref!(peri, rx, tx);
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T::regs().ier().write(|w| {
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// TODO: fix metapac
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w.set_errie(Errie(1));
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w.set_fmpie(0, Fmpie(1));
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w.set_fmpie(1, Fmpie(1));
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w.set_tmeie(Tmeie(1));
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});
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T::regs().mcr().write(|w| {
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// Enable timestamps on rx messages
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w.set_ttcm(true);
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});
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}
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unsafe {
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T::TXInterrupt::unpend();
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T::TXInterrupt::enable();
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T::RX0Interrupt::unpend();
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T::RX0Interrupt::enable();
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T::RX1Interrupt::unpend();
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T::RX1Interrupt::enable();
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T::SCEInterrupt::unpend();
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T::SCEInterrupt::enable();
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}
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rx.set_as_af(rx.af_num(), AFType::Input);
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tx.set_as_af(tx.af_num(), AFType::OutputPushPull);
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T::enable();
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T::reset();
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let can = bxcan::Can::builder(BxcanInstance(peri)).leave_disabled();
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Self { can }
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}
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Self {
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can: bxcan::Can::builder(BxcanInstance(peri)).leave_disabled(),
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pub fn set_bitrate(&mut self, bitrate: u32) {
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let bit_timing = Self::calc_bxcan_timings(T::frequency(), bitrate).unwrap();
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self.can.modify_config().set_bit_timing(bit_timing).leave_disabled();
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}
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/// Queues the message to be sent but exerts backpressure
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pub async fn write(&mut self, frame: &Frame) -> bxcan::TransmitStatus {
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poll_fn(|cx| {
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T::state().tx_waker.register(cx.waker());
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if let Ok(status) = self.can.transmit(frame) {
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return Poll::Ready(status);
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}
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Poll::Pending
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})
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.await
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}
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pub async fn flush(&self, mb: bxcan::Mailbox) {
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poll_fn(|cx| {
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T::state().tx_waker.register(cx.waker());
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if T::regs().tsr().read().tme(mb.index()) {
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return Poll::Ready(());
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}
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Poll::Pending
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})
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.await;
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}
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/// Returns a tuple of the time the message was received and the message frame
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pub async fn read(&mut self) -> Result<(u16, bxcan::Frame), BusError> {
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poll_fn(|cx| {
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T::state().err_waker.register(cx.waker());
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if let Poll::Ready((time, frame)) = T::state().rx_queue.recv().poll_unpin(cx) {
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return Poll::Ready(Ok((time, frame)));
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} else if let Some(err) = self.curr_error() {
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return Poll::Ready(Err(err));
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}
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Poll::Pending
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})
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.await
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}
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fn curr_error(&self) -> Option<BusError> {
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let err = { T::regs().esr().read() };
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if err.boff() {
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return Some(BusError::BusOff);
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} else if err.epvf() {
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return Some(BusError::BusPassive);
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} else if err.ewgf() {
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return Some(BusError::BusWarning);
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} else if let Some(err) = err.lec().into_bus_err() {
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return Some(err);
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}
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None
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}
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unsafe fn receive_fifo(fifo: RxFifo) {
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let state = T::state();
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let regs = T::regs();
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let fifo_idx = match fifo {
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RxFifo::Fifo0 => 0usize,
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RxFifo::Fifo1 => 1usize,
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};
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let rfr = regs.rfr(fifo_idx);
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let fifo = regs.rx(fifo_idx);
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loop {
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// If there are no pending messages, there is nothing to do
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if rfr.read().fmp() == 0 {
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return;
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}
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let rir = fifo.rir().read();
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let id = if rir.ide() == RirIde::STANDARD {
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Id::from(StandardId::new_unchecked(rir.stid()))
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} else {
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let stid = (rir.stid() & 0x7FF) as u32;
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let exid = rir.exid() & 0x3FFFF;
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let id = (stid << 18) | (exid as u32);
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Id::from(ExtendedId::new_unchecked(id))
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};
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let data_len = fifo.rdtr().read().dlc() as usize;
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let mut data: [u8; 8] = [0; 8];
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data[0..4].copy_from_slice(&fifo.rdlr().read().0.to_ne_bytes());
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data[4..8].copy_from_slice(&fifo.rdhr().read().0.to_ne_bytes());
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let time = fifo.rdtr().read().time();
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let frame = Frame::new_data(id, Data::new(&data[0..data_len]).unwrap());
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rfr.modify(|v| v.set_rfom(true));
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/*
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NOTE: consensus was reached that if rx_queue is full, packets should be dropped
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*/
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let _ = state.rx_queue.try_send((time, frame));
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}
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}
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pub const fn calc_bxcan_timings(periph_clock: Hertz, can_bitrate: u32) -> Option<u32> {
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const BS1_MAX: u8 = 16;
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const BS2_MAX: u8 = 8;
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const MAX_SAMPLE_POINT_PERMILL: u16 = 900;
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let periph_clock = periph_clock.0;
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if can_bitrate < 1000 {
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return None;
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}
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// Ref. "Automatic Baudrate Detection in CANopen Networks", U. Koppe, MicroControl GmbH & Co. KG
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// CAN in Automation, 2003
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//
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// According to the source, optimal quanta per bit are:
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// Bitrate Optimal Maximum
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// 1000 kbps 8 10
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// 500 kbps 16 17
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// 250 kbps 16 17
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// 125 kbps 16 17
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let max_quanta_per_bit: u8 = if can_bitrate >= 1_000_000 { 10 } else { 17 };
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// Computing (prescaler * BS):
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// BITRATE = 1 / (PRESCALER * (1 / PCLK) * (1 + BS1 + BS2)) -- See the Reference Manual
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// BITRATE = PCLK / (PRESCALER * (1 + BS1 + BS2)) -- Simplified
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// let:
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// BS = 1 + BS1 + BS2 -- Number of time quanta per bit
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// PRESCALER_BS = PRESCALER * BS
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// ==>
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// PRESCALER_BS = PCLK / BITRATE
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let prescaler_bs = periph_clock / can_bitrate;
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// Searching for such prescaler value so that the number of quanta per bit is highest.
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let mut bs1_bs2_sum = max_quanta_per_bit - 1;
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while (prescaler_bs % (1 + bs1_bs2_sum) as u32) != 0 {
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if bs1_bs2_sum <= 2 {
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return None; // No solution
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}
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bs1_bs2_sum -= 1;
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}
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let prescaler = prescaler_bs / (1 + bs1_bs2_sum) as u32;
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if (prescaler < 1) || (prescaler > 1024) {
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return None; // No solution
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}
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// Now we have a constraint: (BS1 + BS2) == bs1_bs2_sum.
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// We need to find such values so that the sample point is as close as possible to the optimal value,
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// which is 87.5%, which is 7/8.
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//
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// Solve[(1 + bs1)/(1 + bs1 + bs2) == 7/8, bs2] (* Where 7/8 is 0.875, the recommended sample point location *)
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// {{bs2 -> (1 + bs1)/7}}
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//
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// Hence:
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// bs2 = (1 + bs1) / 7
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// bs1 = (7 * bs1_bs2_sum - 1) / 8
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//
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// Sample point location can be computed as follows:
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// Sample point location = (1 + bs1) / (1 + bs1 + bs2)
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//
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// Since the optimal solution is so close to the maximum, we prepare two solutions, and then pick the best one:
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// - With rounding to nearest
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// - With rounding to zero
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let mut bs1 = ((7 * bs1_bs2_sum - 1) + 4) / 8; // Trying rounding to nearest first
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let mut bs2 = bs1_bs2_sum - bs1;
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core::assert!(bs1_bs2_sum > bs1);
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let sample_point_permill = 1000 * ((1 + bs1) / (1 + bs1 + bs2)) as u16;
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if sample_point_permill > MAX_SAMPLE_POINT_PERMILL {
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// Nope, too far; now rounding to zero
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bs1 = (7 * bs1_bs2_sum - 1) / 8;
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bs2 = bs1_bs2_sum - bs1;
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}
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// Check is BS1 and BS2 are in range
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if (bs1 < 1) || (bs1 > BS1_MAX) || (bs2 < 1) || (bs2 > BS2_MAX) {
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return None;
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}
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// Check if final bitrate matches the requested
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if can_bitrate != (periph_clock / (prescaler * (1 + bs1 + bs2) as u32)) {
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return None;
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}
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// One is recommended by DS-015, CANOpen, and DeviceNet
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let sjw = 1;
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// Pack into BTR register values
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Some((sjw - 1) << 24 | (bs1 as u32 - 1) << 16 | (bs2 as u32 - 1) << 20 | (prescaler as u32 - 1))
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}
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}
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enum RxFifo {
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Fifo0,
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Fifo1,
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}
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impl<'d, T: Instance> Drop for Can<'d, T> {
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@ -76,14 +372,52 @@ impl<'d, T: Instance> DerefMut for Can<'d, T> {
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}
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pub(crate) mod sealed {
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use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex;
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use embassy_sync::channel::Channel;
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use embassy_sync::waitqueue::AtomicWaker;
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pub struct State {
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pub tx_waker: AtomicWaker,
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pub err_waker: AtomicWaker,
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pub rx_queue: Channel<CriticalSectionRawMutex, (u16, bxcan::Frame), 32>,
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}
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impl State {
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pub const fn new() -> Self {
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Self {
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tx_waker: AtomicWaker::new(),
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err_waker: AtomicWaker::new(),
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rx_queue: Channel::new(),
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}
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}
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}
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pub trait Instance {
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const REGISTERS: *mut bxcan::RegisterBlock;
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fn regs() -> &'static crate::pac::can::Can;
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fn state() -> &'static State;
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}
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}
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pub trait Instance: sealed::Instance + RccPeripheral {}
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pub trait TXInstance {
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type TXInterrupt: crate::interrupt::typelevel::Interrupt;
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}
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pub trait RX0Instance {
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type RX0Interrupt: crate::interrupt::typelevel::Interrupt;
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}
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pub trait RX1Instance {
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type RX1Interrupt: crate::interrupt::typelevel::Interrupt;
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}
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pub trait SCEInstance {
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type SCEInterrupt: crate::interrupt::typelevel::Interrupt;
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}
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pub trait InterruptableInstance: TXInstance + RX0Instance + RX1Instance + SCEInstance {}
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pub trait Instance: sealed::Instance + RccPeripheral + InterruptableInstance + 'static {}
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pub struct BxcanInstance<'a, T>(PeripheralRef<'a, T>);
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@ -99,10 +433,39 @@ foreach_peripheral!(
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fn regs() -> &'static crate::pac::can::Can {
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&crate::pac::$inst
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}
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fn state() -> &'static sealed::State {
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static STATE: sealed::State = sealed::State::new();
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&STATE
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}
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}
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impl Instance for peripherals::$inst {}
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foreach_interrupt!(
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($inst,can,CAN,TX,$irq:ident) => {
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impl TXInstance for peripherals::$inst {
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type TXInterrupt = crate::interrupt::typelevel::$irq;
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}
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};
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($inst,can,CAN,RX0,$irq:ident) => {
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impl RX0Instance for peripherals::$inst {
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type RX0Interrupt = crate::interrupt::typelevel::$irq;
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}
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};
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($inst,can,CAN,RX1,$irq:ident) => {
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impl RX1Instance for peripherals::$inst {
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type RX1Interrupt = crate::interrupt::typelevel::$irq;
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}
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};
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($inst,can,CAN,SCE,$irq:ident) => {
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impl SCEInstance for peripherals::$inst {
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type SCEInterrupt = crate::interrupt::typelevel::$irq;
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}
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};
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);
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impl InterruptableInstance for peripherals::$inst {}
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};
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);
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@ -143,3 +506,36 @@ foreach_peripheral!(
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pin_trait!(RxPin, Instance);
|
||||
pin_trait!(TxPin, Instance);
|
||||
|
||||
trait Index {
|
||||
fn index(&self) -> usize;
|
||||
}
|
||||
|
||||
impl Index for bxcan::Mailbox {
|
||||
fn index(&self) -> usize {
|
||||
match self {
|
||||
bxcan::Mailbox::Mailbox0 => 0,
|
||||
bxcan::Mailbox::Mailbox1 => 1,
|
||||
bxcan::Mailbox::Mailbox2 => 2,
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
trait IntoBusError {
|
||||
fn into_bus_err(self) -> Option<BusError>;
|
||||
}
|
||||
|
||||
impl IntoBusError for Lec {
|
||||
fn into_bus_err(self) -> Option<BusError> {
|
||||
match self {
|
||||
Lec::STUFF => Some(BusError::Stuff),
|
||||
Lec::FORM => Some(BusError::Form),
|
||||
Lec::ACK => Some(BusError::Acknowledge),
|
||||
Lec::BITRECESSIVE => Some(BusError::BitRecessive),
|
||||
Lec::BITDOMINANT => Some(BusError::BitDominant),
|
||||
Lec::CRC => Some(BusError::Crc),
|
||||
Lec::CUSTOM => Some(BusError::Software),
|
||||
_ => None,
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -4,12 +4,21 @@
|
|||
|
||||
use cortex_m_rt::entry;
|
||||
use defmt::*;
|
||||
use embassy_stm32::bind_interrupts;
|
||||
use embassy_stm32::can::bxcan::filter::Mask32;
|
||||
use embassy_stm32::can::bxcan::{Fifo, Frame, StandardId};
|
||||
use embassy_stm32::can::Can;
|
||||
use embassy_stm32::can::{Can, Rx0InterruptHandler, Rx1InterruptHandler, SceInterruptHandler, TxInterruptHandler};
|
||||
use embassy_stm32::gpio::{Input, Pull};
|
||||
use embassy_stm32::peripherals::CAN1;
|
||||
use {defmt_rtt as _, panic_probe as _};
|
||||
|
||||
bind_interrupts!(struct Irqs {
|
||||
CAN1_RX0 => Rx0InterruptHandler<CAN1>;
|
||||
CAN1_RX1 => Rx1InterruptHandler<CAN1>;
|
||||
CAN1_SCE => SceInterruptHandler<CAN1>;
|
||||
CAN1_TX => TxInterruptHandler<CAN1>;
|
||||
});
|
||||
|
||||
#[entry]
|
||||
fn main() -> ! {
|
||||
info!("Hello World!");
|
||||
|
|
@ -23,7 +32,7 @@ fn main() -> ! {
|
|||
let rx_pin = Input::new(&mut p.PA11, Pull::Up);
|
||||
core::mem::forget(rx_pin);
|
||||
|
||||
let mut can = Can::new(p.CAN1, p.PA11, p.PA12);
|
||||
let mut can = Can::new(p.CAN1, p.PA11, p.PA12, Irqs);
|
||||
|
||||
can.modify_filters().enable_bank(0, Fifo::Fifo0, Mask32::accept_all());
|
||||
|
||||
|
|
|
|||
|
|
@ -7,7 +7,7 @@ autobins = false
|
|||
|
||||
[features]
|
||||
stm32f103c8 = ["embassy-stm32/stm32f103c8", "not-gpdma"] # Blue Pill
|
||||
stm32f429zi = ["embassy-stm32/stm32f429zi", "chrono", "not-gpdma"] # Nucleo "sdmmc"
|
||||
stm32f429zi = ["embassy-stm32/stm32f429zi", "chrono", "can", "not-gpdma"] # Nucleo "sdmmc"
|
||||
stm32g071rb = ["embassy-stm32/stm32g071rb", "not-gpdma"] # Nucleo
|
||||
stm32c031c6 = ["embassy-stm32/stm32c031c6", "not-gpdma"] # Nucleo
|
||||
stm32g491re = ["embassy-stm32/stm32g491re", "not-gpdma"] # Nucleo
|
||||
|
|
@ -18,6 +18,7 @@ stm32u585ai = ["embassy-stm32/stm32u585ai"] # IoT board
|
|||
|
||||
sdmmc = []
|
||||
chrono = ["embassy-stm32/chrono", "dep:chrono"]
|
||||
can = []
|
||||
ble = ["dep:embassy-stm32-wpan"]
|
||||
not-gpdma = []
|
||||
|
||||
|
|
@ -52,6 +53,11 @@ name = "tl_mbox"
|
|||
path = "src/bin/tl_mbox.rs"
|
||||
required-features = [ "ble",]
|
||||
|
||||
[[bin]]
|
||||
name = "can"
|
||||
path = "src/bin/can.rs"
|
||||
required-features = [ "can",]
|
||||
|
||||
[[bin]]
|
||||
name = "gpio"
|
||||
path = "src/bin/gpio.rs"
|
||||
|
|
|
|||
78
tests/stm32/src/bin/can.rs
Normal file
78
tests/stm32/src/bin/can.rs
Normal file
|
|
@ -0,0 +1,78 @@
|
|||
#![no_std]
|
||||
#![no_main]
|
||||
#![feature(type_alias_impl_trait)]
|
||||
|
||||
// required-features: can
|
||||
|
||||
#[path = "../common.rs"]
|
||||
mod common;
|
||||
use common::*;
|
||||
use embassy_executor::Spawner;
|
||||
use embassy_stm32::bind_interrupts;
|
||||
use embassy_stm32::can::bxcan::filter::Mask32;
|
||||
use embassy_stm32::can::bxcan::{Fifo, Frame, StandardId};
|
||||
use embassy_stm32::can::{Can, Rx0InterruptHandler, Rx1InterruptHandler, SceInterruptHandler, TxInterruptHandler};
|
||||
use embassy_stm32::gpio::{Input, Pull};
|
||||
use embassy_stm32::peripherals::CAN1;
|
||||
use {defmt_rtt as _, panic_probe as _};
|
||||
|
||||
bind_interrupts!(struct Irqs {
|
||||
CAN1_RX0 => Rx0InterruptHandler<CAN1>;
|
||||
CAN1_RX1 => Rx1InterruptHandler<CAN1>;
|
||||
CAN1_SCE => SceInterruptHandler<CAN1>;
|
||||
CAN1_TX => TxInterruptHandler<CAN1>;
|
||||
});
|
||||
|
||||
#[embassy_executor::main]
|
||||
async fn main(_spawner: Spawner) {
|
||||
let mut p = embassy_stm32::init(config());
|
||||
info!("Hello World!");
|
||||
|
||||
// HW is connected as follows:
|
||||
// PB13 -> PD0
|
||||
// PB12 -> PD1
|
||||
|
||||
// The next two lines are a workaround for testing without transceiver.
|
||||
// To synchronise to the bus the RX input needs to see a high level.
|
||||
// Use `mem::forget()` to release the borrow on the pin but keep the
|
||||
// pull-up resistor enabled.
|
||||
let rx_pin = Input::new(&mut p.PD0, Pull::Up);
|
||||
core::mem::forget(rx_pin);
|
||||
|
||||
let mut can = Can::new(p.CAN1, p.PD0, p.PD1, Irqs);
|
||||
|
||||
info!("Configuring can...");
|
||||
|
||||
can.modify_filters().enable_bank(0, Fifo::Fifo0, Mask32::accept_all());
|
||||
|
||||
can.set_bitrate(1_000_000);
|
||||
can.modify_config()
|
||||
.set_loopback(true) // Receive own frames
|
||||
.set_silent(true)
|
||||
// .set_bit_timing(0x001c0003)
|
||||
.enable();
|
||||
|
||||
info!("Can configured");
|
||||
|
||||
let mut i: u8 = 0;
|
||||
loop {
|
||||
let tx_frame = Frame::new_data(unwrap!(StandardId::new(i as _)), [i]);
|
||||
|
||||
info!("Transmitting frame...");
|
||||
can.write(&tx_frame).await;
|
||||
|
||||
info!("Receiving frame...");
|
||||
let (time, rx_frame) = can.read().await.unwrap();
|
||||
|
||||
info!("loopback time {}", time);
|
||||
info!("loopback frame {=u8}", rx_frame.data().unwrap()[0]);
|
||||
|
||||
i += 1;
|
||||
if i > 10 {
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
info!("Test OK");
|
||||
cortex_m::asm::bkpt();
|
||||
}
|
||||
Loading…
Reference in a new issue