Rearrange new:s
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parent
27905f1be1
commit
3fce6ec649
2 changed files with 128 additions and 64 deletions
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@ -65,66 +65,6 @@ fn calc_prescs(freq: u32) -> (u8, u8) {
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}
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impl<'d, T: Instance, M: Mode> Spi<'d, T, M> {
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pub fn new_blocking(
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inner: impl Peripheral<P = T> + 'd,
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clk: impl Peripheral<P = impl ClkPin<T> + 'd> + 'd,
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mosi: impl Peripheral<P = impl MosiPin<T> + 'd> + 'd,
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miso: impl Peripheral<P = impl MisoPin<T> + 'd> + 'd,
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config: Config,
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) -> Self {
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into_ref!(clk, mosi, miso);
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Self::new_inner(
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inner,
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None,
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None,
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Some(clk.map_into()),
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Some(mosi.map_into()),
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Some(miso.map_into()),
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None,
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config,
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)
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}
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pub fn new_txonly(
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inner: impl Peripheral<P = T> + 'd,
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tx_dma: Option<PeripheralRef<'d, AnyChannel>>,
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clk: impl Peripheral<P = impl ClkPin<T> + 'd> + 'd,
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mosi: impl Peripheral<P = impl MosiPin<T> + 'd> + 'd,
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config: Config,
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) -> Self {
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into_ref!(clk, mosi);
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Self::new_inner(
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inner,
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tx_dma,
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None,
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Some(clk.map_into()),
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Some(mosi.map_into()),
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None,
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None,
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config,
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)
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}
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pub fn new_rxonly(
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inner: impl Peripheral<P = T> + 'd,
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rx_dma: Option<PeripheralRef<'d, AnyChannel>>,
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clk: impl Peripheral<P = impl ClkPin<T> + 'd> + 'd,
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miso: impl Peripheral<P = impl MisoPin<T> + 'd> + 'd,
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config: Config,
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) -> Self {
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into_ref!(clk, miso);
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Self::new_inner(
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inner,
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None,
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rx_dma,
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Some(clk.map_into()),
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None,
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Some(miso.map_into()),
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None,
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config,
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)
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}
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fn new_inner(
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inner: impl Peripheral<P = T> + 'd,
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tx_dma: Option<PeripheralRef<'d, AnyChannel>>,
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@ -261,6 +201,66 @@ impl<'d, T: Instance, M: Mode> Spi<'d, T, M> {
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}
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}
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impl<'d, T: Instance> Spi<'d, T, Blocking> {
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pub fn new_blocking(
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inner: impl Peripheral<P = T> + 'd,
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clk: impl Peripheral<P = impl ClkPin<T> + 'd> + 'd,
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mosi: impl Peripheral<P = impl MosiPin<T> + 'd> + 'd,
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miso: impl Peripheral<P = impl MisoPin<T> + 'd> + 'd,
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config: Config,
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) -> Self {
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into_ref!(clk, mosi, miso);
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Self::new_inner(
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inner,
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None,
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None,
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Some(clk.map_into()),
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Some(mosi.map_into()),
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Some(miso.map_into()),
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None,
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config,
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)
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}
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pub fn new_blocking_txonly(
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inner: impl Peripheral<P = T> + 'd,
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clk: impl Peripheral<P = impl ClkPin<T> + 'd> + 'd,
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mosi: impl Peripheral<P = impl MosiPin<T> + 'd> + 'd,
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config: Config,
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) -> Self {
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into_ref!(clk, mosi);
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Self::new_inner(
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inner,
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None,
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None,
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Some(clk.map_into()),
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Some(mosi.map_into()),
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None,
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None,
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config,
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)
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}
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pub fn new_blocking_rxonly(
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inner: impl Peripheral<P = T> + 'd,
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clk: impl Peripheral<P = impl ClkPin<T> + 'd> + 'd,
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miso: impl Peripheral<P = impl MisoPin<T> + 'd> + 'd,
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config: Config,
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) -> Self {
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into_ref!(clk, miso);
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Self::new_inner(
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inner,
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None,
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None,
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Some(clk.map_into()),
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None,
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Some(miso.map_into()),
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None,
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config,
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)
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}
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}
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impl<'d, T: Instance> Spi<'d, T, Async> {
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pub fn new(
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inner: impl Peripheral<P = T> + 'd,
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@ -284,6 +284,46 @@ impl<'d, T: Instance> Spi<'d, T, Async> {
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)
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}
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pub fn new_txonly(
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inner: impl Peripheral<P = T> + 'd,
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tx_dma: impl Peripheral<P = impl Channel> + 'd,
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clk: impl Peripheral<P = impl ClkPin<T> + 'd> + 'd,
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mosi: impl Peripheral<P = impl MosiPin<T> + 'd> + 'd,
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config: Config,
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) -> Self {
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into_ref!(tx_dma, clk, mosi);
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Self::new_inner(
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inner,
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Some(tx_dma.map_into()),
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None,
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Some(clk.map_into()),
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Some(mosi.map_into()),
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None,
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None,
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config,
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)
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}
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pub fn new_rxonly(
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inner: impl Peripheral<P = T> + 'd,
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rx_dma: impl Peripheral<P = impl Channel> + 'd,
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clk: impl Peripheral<P = impl ClkPin<T> + 'd> + 'd,
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miso: impl Peripheral<P = impl MisoPin<T> + 'd> + 'd,
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config: Config,
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) -> Self {
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into_ref!(rx_dma, clk, miso);
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Self::new_inner(
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inner,
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None,
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Some(rx_dma.map_into()),
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Some(clk.map_into()),
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None,
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Some(miso.map_into()),
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None,
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config,
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)
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}
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pub async fn write(&mut self, buffer: &[u8]) -> Result<(), Error> {
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let (from_ptr, len) = crate::dma::slice_ptr_parts(buffer);
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let ch = self.tx_dma.as_mut().unwrap();
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@ -293,7 +333,13 @@ impl<'d, T: Instance> Spi<'d, T, Async> {
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});
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// If we don't assign future to a variable, the data register pointer
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// is held across an await and makes the future non-Send.
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crate::dma::write(ch, from_ptr as *const u32, self.inner.regs().dr().ptr() as *mut _, len, T::TX_DREQ)
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crate::dma::write(
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ch,
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from_ptr as *const u32,
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self.inner.regs().dr().ptr() as *mut _,
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len,
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T::TX_DREQ,
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)
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};
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transfer.await;
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Ok(())
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@ -308,7 +354,13 @@ impl<'d, T: Instance> Spi<'d, T, Async> {
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});
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// If we don't assign future to a variable, the data register pointer
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// is held across an await and makes the future non-Send.
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crate::dma::read(ch, self.inner.regs().dr().ptr() as *const _, to_ptr as *mut u32, len, T::RX_DREQ)
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crate::dma::read(
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ch,
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self.inner.regs().dr().ptr() as *const _,
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to_ptr as *mut u32,
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len,
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T::RX_DREQ,
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)
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};
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transfer.await;
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Ok(())
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@ -128,7 +128,13 @@ impl<'d, T: Instance> UartTx<'d, T, Async> {
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});
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// If we don't assign future to a variable, the data register pointer
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// is held across an await and makes the future non-Send.
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crate::dma::write(ch, from_ptr as *const u32, T::regs().uartdr().ptr() as *mut _, len, T::TX_DREQ)
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crate::dma::write(
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ch,
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from_ptr as *const u32,
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T::regs().uartdr().ptr() as *mut _,
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len,
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T::TX_DREQ,
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)
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};
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transfer.await;
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Ok(())
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@ -182,7 +188,13 @@ impl<'d, T: Instance> UartRx<'d, T, Async> {
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});
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// If we don't assign future to a variable, the data register pointer
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// is held across an await and makes the future non-Send.
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crate::dma::read(ch, T::regs().uartdr().ptr() as *const _, to_ptr as *mut u32, len, T::RX_DREQ)
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crate::dma::read(
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ch,
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T::regs().uartdr().ptr() as *const _,
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to_ptr as *mut u32,
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len,
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T::RX_DREQ,
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)
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};
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transfer.await;
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Ok(())
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