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stm32: extract backupdomain into mod

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This commit is contained in:
xoviat 2023-08-27 09:07:34 -05:00
parent 48085939e7
commit 4caa8497fc
9 changed files with 185 additions and 168 deletions
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168
embassy-stm32/src/rcc/bd.rs Normal file
View file

@ -0,0 +1,168 @@
#[derive(Copy, Clone, Debug, PartialEq)]
#[repr(u8)]
pub enum RtcClockSource {
/// 00: No clock
NoClock = 0b00,
/// 01: LSE oscillator clock used as RTC clock
LSE = 0b01,
/// 10: LSI oscillator clock used as RTC clock
LSI = 0b10,
/// 11: HSE oscillator clock divided by 32 used as RTC clock
HSE = 0b11,
}
pub struct BackupDomain {}
impl BackupDomain {
#[cfg(any(
rtc_v2f0, rtc_v2f2, rtc_v2f3, rtc_v2f4, rtc_v2f7, rtc_v2h7, rtc_v2l0, rtc_v2l1, rtc_v2l4, rtc_v2wb
))]
fn unlock_registers() {
#[cfg(any(rtc_v2f2, rtc_v2f3, rtc_v2l1))]
let cr = crate::pac::PWR.cr();
#[cfg(any(rtc_v2f4, rtc_v2f7, rtc_v2h7, rtc_v2l4, rtc_v2wb))]
let cr = crate::pac::PWR.cr1();
// TODO: Missing from PAC for l0 and f0?
#[cfg(not(any(rtc_v2f0, rtc_v2l0)))]
{
if !cr.read().dbp() {
cr.modify(|w| w.set_dbp(true));
while !cr.read().dbp() {}
}
}
}
#[cfg(any(rtc_v3, rtc_v3u5))]
fn unlock_registers() {
// Unlock the backup domain
#[cfg(not(any(rtc_v3u5, rcc_wl5, rcc_wle)))]
{
if !crate::pac::PWR.cr1().read().dbp() {
crate::pac::PWR.cr1().modify(|w| w.set_dbp(true));
while !crate::pac::PWR.cr1().read().dbp() {}
}
}
#[cfg(any(rcc_wl5, rcc_wle))]
{
use crate::pac::pwr::vals::Dbp;
if crate::pac::PWR.cr1().read().dbp() != Dbp::ENABLED {
crate::pac::PWR.cr1().modify(|w| w.set_dbp(Dbp::ENABLED));
while crate::pac::PWR.cr1().read().dbp() != Dbp::ENABLED {}
}
}
}
#[cfg(any(
rtc_v2f0, rtc_v2f2, rtc_v2f3, rtc_v2f4, rtc_v2f7, rtc_v2h7, rtc_v2l0, rtc_v2l1, rtc_v2l4, rtc_v2wb
))]
pub fn set_rtc_clock_source(clock_source: RtcClockSource) {
#[cfg(not(rtc_v2wb))]
use stm32_metapac::rcc::vals::Rtcsel;
#[cfg(not(any(rtc_v2l0, rtc_v2l1)))]
let cr = crate::pac::RCC.bdcr();
#[cfg(any(rtc_v2l0, rtc_v2l1))]
let cr = crate::pac::RCC.csr();
Self::unlock_registers();
cr.modify(|w| {
// Select RTC source
#[cfg(not(rtc_v2wb))]
w.set_rtcsel(Rtcsel::from_bits(clock_source as u8));
#[cfg(rtc_v2wb)]
w.set_rtcsel(clock_source as u8);
});
}
#[cfg(any(rtc_v3, rtc_v3u5))]
pub fn set_rtc_clock_source(clock_source: RtcClockSource) {
let clock_source = clock_source as u8;
#[cfg(not(any(rcc_wl5, rcc_wle)))]
let clock_source = crate::pac::rcc::vals::Rtcsel::from_bits(clock_source);
Self::unlock_registers();
crate::pac::RCC.bdcr().modify(|w| {
// Select RTC source
w.set_rtcsel(clock_source);
});
}
#[cfg(any(
rtc_v2f0, rtc_v2f2, rtc_v2f3, rtc_v2f4, rtc_v2f7, rtc_v2h7, rtc_v2l0, rtc_v2l1, rtc_v2l4, rtc_v2wb
))]
pub fn enable_rtc() {
#[cfg(not(any(rtc_v2l0, rtc_v2l1)))]
let reg = crate::pac::RCC.bdcr().read();
#[cfg(any(rtc_v2l0, rtc_v2l1))]
let reg = crate::pac::RCC.csr().read();
#[cfg(any(rtc_v2h7, rtc_v2l4, rtc_v2wb))]
assert!(!reg.lsecsson(), "RTC is not compatible with LSE CSS, yet.");
if !reg.rtcen() {
Self::unlock_registers();
#[cfg(not(any(rtc_v2l0, rtc_v2l1, rtc_v2f2)))]
crate::pac::RCC.bdcr().modify(|w| w.set_bdrst(true));
#[cfg(not(any(rtc_v2l0, rtc_v2l1)))]
let cr = crate::pac::RCC.bdcr();
#[cfg(any(rtc_v2l0, rtc_v2l1))]
let cr = crate::pac::RCC.csr();
cr.modify(|w| {
// Reset
#[cfg(not(any(rtc_v2l0, rtc_v2l1)))]
w.set_bdrst(false);
w.set_rtcen(true);
w.set_rtcsel(reg.rtcsel());
// Restore bcdr
#[cfg(any(rtc_v2l4, rtc_v2wb))]
w.set_lscosel(reg.lscosel());
#[cfg(any(rtc_v2l4, rtc_v2wb))]
w.set_lscoen(reg.lscoen());
w.set_lseon(reg.lseon());
#[cfg(any(rtc_v2f0, rtc_v2f7, rtc_v2h7, rtc_v2l4, rtc_v2wb))]
w.set_lsedrv(reg.lsedrv());
w.set_lsebyp(reg.lsebyp());
});
}
}
#[cfg(any(rtc_v3, rtc_v3u5))]
pub fn enable_rtc() {
let bdcr = crate::pac::RCC.bdcr();
let reg = bdcr.read();
assert!(!reg.lsecsson(), "RTC is not compatible with LSE CSS, yet.");
if !reg.rtcen() {
Self::unlock_registers();
bdcr.modify(|w| w.set_bdrst(true));
bdcr.modify(|w| {
// Reset
w.set_bdrst(false);
w.set_rtcen(true);
w.set_rtcsel(reg.rtcsel());
// Restore bcdr
w.set_lscosel(reg.lscosel());
w.set_lscoen(reg.lscoen());
w.set_lseon(reg.lseon());
w.set_lsedrv(reg.lsedrv());
w.set_lsebyp(reg.lsebyp());
});
}
}
}

4
embassy-stm32/src/rcc/f4.rs
View file

@ -8,8 +8,8 @@ use crate::gpio::sealed::AFType;
use crate::gpio::Speed;
use crate::pac::rcc::vals::{Hpre, Ppre, Sw};
use crate::pac::{FLASH, PWR, RCC};
use crate::rcc::bd::{BackupDomain, RtcClockSource};
use crate::rcc::{set_freqs, Clocks};
use crate::rtc::{Rtc, RtcClockSource};
use crate::time::Hertz;
use crate::{peripherals, Peripheral};
@ -470,7 +470,7 @@ pub(crate) unsafe fn init(config: Config) {
}
config.rtc.map(|clock_source| {
Rtc::set_clock_source(clock_source);
BackupDomain::set_rtc_clock_source(clock_source);
});
let rtc = match config.rtc {

6
embassy-stm32/src/rcc/l4.rs
View file

@ -9,8 +9,8 @@ use crate::gpio::sealed::AFType;
use crate::gpio::Speed;
use crate::pac::rcc::vals::{Hpre, Msirange, Pllsrc, Ppre, Sw};
use crate::pac::{FLASH, PWR, RCC};
use crate::rcc::bd::{BackupDomain, RtcClockSource as RCS};
use crate::rcc::{set_freqs, Clocks};
use crate::rtc::{Rtc, RtcClockSource as RCS};
use crate::time::Hertz;
use crate::{peripherals, Peripheral};
@ -429,7 +429,7 @@ pub(crate) unsafe fn init(config: Config) {
// Wait until LSE is running
while !RCC.bdcr().read().lserdy() {}
Rtc::set_clock_source(RCS::LSE);
BackupDomain::set_rtc_clock_source(RCS::LSE);
}
RtcClockSource::LSI32 => {
// Turn on the internal 32 kHz LSI oscillator
@ -438,7 +438,7 @@ pub(crate) unsafe fn init(config: Config) {
// Wait until LSI is running
while !RCC.csr().read().lsirdy() {}
Rtc::set_clock_source(RCS::LSI);
BackupDomain::set_rtc_clock_source(RCS::LSI);
}
}

1
embassy-stm32/src/rcc/mod.rs
View file

@ -1,5 +1,6 @@
#![macro_use]
pub(crate) mod bd;
pub mod bus;
use core::mem::MaybeUninit;

6
embassy-stm32/src/rcc/wb.rs
View file

@ -1,6 +1,6 @@
pub use super::bus::{AHBPrescaler, APBPrescaler};
use crate::rcc::bd::{BackupDomain, RtcClockSource};
use crate::rcc::Clocks;
use crate::rtc::{Rtc, RtcClockSource};
use crate::time::{khz, mhz, Hertz};
/// Most of clock setup is copied from stm32l0xx-hal, and adopted to the generated PAC,
@ -375,5 +375,7 @@ pub(crate) fn configure_clocks(config: &Config) {
w.set_shdhpre(config.ahb3_pre.into());
});
config.rtc.map(|clock_source| Rtc::set_clock_source(clock_source));
config
.rtc
.map(|clock_source| BackupDomain::set_rtc_clock_source(clock_source));
}

6
embassy-stm32/src/rcc/wl.rs
View file

@ -1,8 +1,8 @@
pub use super::bus::{AHBPrescaler, APBPrescaler, VoltageScale};
use crate::pac::pwr::vals::Dbp;
use crate::pac::{FLASH, PWR, RCC};
use crate::rcc::bd::{BackupDomain, RtcClockSource as RCS};
use crate::rcc::{set_freqs, Clocks};
use crate::rtc::{Rtc, RtcClockSource as RCS};
use crate::time::Hertz;
/// Most of clock setup is copied from stm32l0xx-hal, and adopted to the generated PAC,
@ -231,7 +231,7 @@ pub(crate) unsafe fn init(config: Config) {
// Wait until LSE is running
while !RCC.bdcr().read().lserdy() {}
Rtc::set_clock_source(RCS::LSE);
BackupDomain::set_rtc_clock_source(RCS::LSE);
}
RtcClockSource::LSI32 => {
// Turn on the internal 32 kHz LSI oscillator
@ -240,7 +240,7 @@ pub(crate) unsafe fn init(config: Config) {
// Wait until LSI is running
while !RCC.csr().read().lsirdy() {}
Rtc::set_clock_source(RCS::LSI);
BackupDomain::set_rtc_clock_source(RCS::LSI);
}
}

16
embassy-stm32/src/rtc/mod.rs
View file

@ -10,6 +10,7 @@ use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex;
use embassy_sync::blocking_mutex::Mutex;
pub use self::datetime::{DateTime, DayOfWeek, Error as DateTimeError};
use crate::rcc::bd::BackupDomain;
/// refer to AN4759 to compare features of RTC2 and RTC3
#[cfg_attr(any(rtc_v1), path = "v1.rs")]
@ -107,19 +108,6 @@ pub struct Rtc {
stop_time: Mutex<CriticalSectionRawMutex, Cell<Option<RtcInstant>>>,
}
#[derive(Copy, Clone, Debug, PartialEq)]
#[repr(u8)]
pub enum RtcClockSource {
/// 00: No clock
NoClock = 0b00,
/// 01: LSE oscillator clock used as RTC clock
LSE = 0b01,
/// 10: LSI oscillator clock used as RTC clock
LSI = 0b10,
/// 11: HSE oscillator clock divided by 32 used as RTC clock
HSE = 0b11,
}
#[derive(Copy, Clone, PartialEq)]
pub struct RtcConfig {
/// Asynchronous prescaler factor
@ -189,7 +177,7 @@ impl Rtc {
stop_time: Mutex::const_new(CriticalSectionRawMutex::new(), Cell::new(None)),
};
Self::enable();
BackupDomain::enable_rtc();
rtc_struct.configure(rtc_config);
rtc_struct.rtc_config = rtc_config;

81
embassy-stm32/src/rtc/v2.rs
View file

@ -2,7 +2,7 @@ use stm32_metapac::rtc::vals::{Init, Osel, Pol};
#[cfg(feature = "low-power")]
use super::RtcInstant;
use super::{sealed, RtcClockSource, RtcConfig};
use super::{sealed, RtcConfig};
use crate::pac::rtc::Rtc;
use crate::peripherals::RTC;
use crate::rtc::sealed::Instance;
@ -73,22 +73,6 @@ impl WakeupPrescaler {
}
impl super::Rtc {
fn unlock_registers() {
#[cfg(any(rtc_v2f2, rtc_v2f3, rtc_v2l1))]
let cr = crate::pac::PWR.cr();
#[cfg(any(rtc_v2f4, rtc_v2f7, rtc_v2h7, rtc_v2l4, rtc_v2wb))]
let cr = crate::pac::PWR.cr1();
// TODO: Missing from PAC for l0 and f0?
#[cfg(not(any(rtc_v2f0, rtc_v2l0)))]
{
if !cr.read().dbp() {
cr.modify(|w| w.set_dbp(true));
while !cr.read().dbp() {}
}
}
}
#[cfg(feature = "low-power")]
/// start the wakeup alarm and wtih a duration that is as close to but less than
/// the requested duration, and record the instant the wakeup alarm was started
@ -155,69 +139,6 @@ impl super::Rtc {
})
}
#[allow(dead_code)]
pub(crate) fn set_clock_source(clock_source: RtcClockSource) {
#[cfg(not(rtc_v2wb))]
use stm32_metapac::rcc::vals::Rtcsel;
#[cfg(not(any(rtc_v2l0, rtc_v2l1)))]
let cr = crate::pac::RCC.bdcr();
#[cfg(any(rtc_v2l0, rtc_v2l1))]
let cr = crate::pac::RCC.csr();
Self::unlock_registers();
cr.modify(|w| {
// Select RTC source
#[cfg(not(rtc_v2wb))]
w.set_rtcsel(Rtcsel::from_bits(clock_source as u8));
#[cfg(rtc_v2wb)]
w.set_rtcsel(clock_source as u8);
});
}
pub(super) fn enable() {
#[cfg(not(any(rtc_v2l0, rtc_v2l1)))]
let reg = crate::pac::RCC.bdcr().read();
#[cfg(any(rtc_v2l0, rtc_v2l1))]
let reg = crate::pac::RCC.csr().read();
#[cfg(any(rtc_v2h7, rtc_v2l4, rtc_v2wb))]
assert!(!reg.lsecsson(), "RTC is not compatible with LSE CSS, yet.");
if !reg.rtcen() {
Self::unlock_registers();
#[cfg(not(any(rtc_v2l0, rtc_v2l1, rtc_v2f2)))]
crate::pac::RCC.bdcr().modify(|w| w.set_bdrst(true));
#[cfg(not(any(rtc_v2l0, rtc_v2l1)))]
let cr = crate::pac::RCC.bdcr();
#[cfg(any(rtc_v2l0, rtc_v2l1))]
let cr = crate::pac::RCC.csr();
cr.modify(|w| {
// Reset
#[cfg(not(any(rtc_v2l0, rtc_v2l1)))]
w.set_bdrst(false);
w.set_rtcen(true);
w.set_rtcsel(reg.rtcsel());
// Restore bcdr
#[cfg(any(rtc_v2l4, rtc_v2wb))]
w.set_lscosel(reg.lscosel());
#[cfg(any(rtc_v2l4, rtc_v2wb))]
w.set_lscoen(reg.lscoen());
w.set_lseon(reg.lseon());
#[cfg(any(rtc_v2f0, rtc_v2f7, rtc_v2h7, rtc_v2l4, rtc_v2wb))]
w.set_lsedrv(reg.lsedrv());
w.set_lsebyp(reg.lsebyp());
});
}
}
/// Applies the RTC config
/// It this changes the RTC clock source the time will be reset
pub(super) fn configure(&mut self, rtc_config: RtcConfig) {

65
embassy-stm32/src/rtc/v3.rs
View file

@ -1,74 +1,11 @@
use stm32_metapac::rtc::vals::{Calp, Calw16, Calw8, Fmt, Init, Key, Osel, Pol, TampalrmPu, TampalrmType};
use super::{sealed, RtcCalibrationCyclePeriod, RtcClockSource, RtcConfig};
use super::{sealed, RtcCalibrationCyclePeriod, RtcConfig};
use crate::pac::rtc::Rtc;
use crate::peripherals::RTC;
use crate::rtc::sealed::Instance;
impl super::Rtc {
fn unlock_registers() {
// Unlock the backup domain
#[cfg(not(any(rtc_v3u5, rcc_wl5, rcc_wle)))]
{
if !crate::pac::PWR.cr1().read().dbp() {
crate::pac::PWR.cr1().modify(|w| w.set_dbp(true));
while !crate::pac::PWR.cr1().read().dbp() {}
}
}
#[cfg(any(rcc_wl5, rcc_wle))]
{
use crate::pac::pwr::vals::Dbp;
if crate::pac::PWR.cr1().read().dbp() != Dbp::ENABLED {
crate::pac::PWR.cr1().modify(|w| w.set_dbp(Dbp::ENABLED));
while crate::pac::PWR.cr1().read().dbp() != Dbp::ENABLED {}
}
}
}
#[allow(dead_code)]
pub(crate) fn set_clock_source(clock_source: RtcClockSource) {
let clock_source = clock_source as u8;
#[cfg(not(any(rcc_wl5, rcc_wle)))]
let clock_source = crate::pac::rcc::vals::Rtcsel::from_bits(clock_source);
Self::unlock_registers();
crate::pac::RCC.bdcr().modify(|w| {
// Select RTC source
w.set_rtcsel(clock_source);
});
}
pub(super) fn enable() {
let bdcr = crate::pac::RCC.bdcr();
let reg = bdcr.read();
assert!(!reg.lsecsson(), "RTC is not compatible with LSE CSS, yet.");
if !reg.rtcen() {
Self::unlock_registers();
bdcr.modify(|w| w.set_bdrst(true));
bdcr.modify(|w| {
// Reset
w.set_bdrst(false);
w.set_rtcen(true);
w.set_rtcsel(reg.rtcsel());
// Restore bcdr
w.set_lscosel(reg.lscosel());
w.set_lscoen(reg.lscoen());
w.set_lseon(reg.lseon());
w.set_lsedrv(reg.lsedrv());
w.set_lsebyp(reg.lsebyp());
});
}
}
/// Applies the RTC config
/// It this changes the RTC clock source the time will be reset
pub(super) fn configure(&mut self, rtc_config: RtcConfig) {