rcc/bd: consolidate mod
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f28ab18d7b
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3 changed files with 46 additions and 80 deletions
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@ -58,7 +58,7 @@ sdio-host = "0.5.0"
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embedded-sdmmc = { git = "https://github.com/embassy-rs/embedded-sdmmc-rs", rev = "a4f293d3a6f72158385f79c98634cb8a14d0d2fc", optional = true }
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embedded-sdmmc = { git = "https://github.com/embassy-rs/embedded-sdmmc-rs", rev = "a4f293d3a6f72158385f79c98634cb8a14d0d2fc", optional = true }
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critical-section = "1.1"
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critical-section = "1.1"
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atomic-polyfill = "1.0.1"
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atomic-polyfill = "1.0.1"
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stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-2b87e34c661e19ff6dc603fabfe7fe99ab7261f7" }
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stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-9a61a1f090462df8bd1751f89951f04934fdceb3" }
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vcell = "0.1.3"
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vcell = "0.1.3"
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bxcan = "0.7.0"
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bxcan = "0.7.0"
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nb = "1.0.0"
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nb = "1.0.0"
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@ -77,7 +77,7 @@ critical-section = { version = "1.1", features = ["std"] }
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[build-dependencies]
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[build-dependencies]
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proc-macro2 = "1.0.36"
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proc-macro2 = "1.0.36"
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quote = "1.0.15"
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quote = "1.0.15"
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stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-2b87e34c661e19ff6dc603fabfe7fe99ab7261f7", default-features = false, features = ["metadata"]}
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stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-9a61a1f090462df8bd1751f89951f04934fdceb3", default-features = false, features = ["metadata"]}
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[features]
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[features]
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default = ["rt"]
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default = ["rt"]
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@ -12,86 +12,67 @@ pub enum RtcClockSource {
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HSE = 0b11,
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HSE = 0b11,
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}
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}
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#[cfg(not(any(rtc_v2l0, rtc_v2l1)))]
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type Bdcr = crate::pac::rcc::regs::Bdcr;
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#[cfg(any(rtc_v2l0, rtc_v2l1))]
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type Bdcr = crate::pac::rcc::regs::Csr;
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#[allow(dead_code)]
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#[allow(dead_code)]
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pub struct BackupDomain {}
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pub struct BackupDomain {}
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impl BackupDomain {
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impl BackupDomain {
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#[cfg(any(
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#[cfg(any(
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rtc_v2f0, rtc_v2f2, rtc_v2f3, rtc_v2f4, rtc_v2f7, rtc_v2h7, rtc_v2l0, rtc_v2l1, rtc_v2l4, rtc_v2wb
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rtc_v2f0, rtc_v2f2, rtc_v2f3, rtc_v2f4, rtc_v2f7, rtc_v2h7, rtc_v2l0, rtc_v2l1, rtc_v2l4, rtc_v2wb, rtc_v3,
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rtc_v3u5
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))]
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))]
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#[allow(dead_code)]
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#[allow(dead_code)]
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fn unlock_registers() {
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fn modify<R>(f: impl FnOnce(&mut Bdcr) -> R) -> R {
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#[cfg(any(rtc_v2f2, rtc_v2f3, rtc_v2l1))]
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#[cfg(any(rtc_v2f2, rtc_v2f3, rtc_v2l1))]
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let cr = crate::pac::PWR.cr();
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let cr = crate::pac::PWR.cr();
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#[cfg(any(rtc_v2f4, rtc_v2f7, rtc_v2h7, rtc_v2l4, rtc_v2wb))]
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#[cfg(any(rtc_v2f4, rtc_v2f7, rtc_v2h7, rtc_v2l4, rtc_v2wb, rtc_v3, rtc_v3u5))]
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let cr = crate::pac::PWR.cr1();
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let cr = crate::pac::PWR.cr1();
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// TODO: Missing from PAC for l0 and f0?
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// TODO: Missing from PAC for l0 and f0?
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#[cfg(not(any(rtc_v2f0, rtc_v2l0)))]
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#[cfg(not(any(rtc_v2f0, rtc_v2l0, rtc_v3u5)))]
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{
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{
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if !cr.read().dbp() {
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cr.modify(|w| w.set_dbp(true));
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cr.modify(|w| w.set_dbp(true));
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while !cr.read().dbp() {}
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while !cr.read().dbp() {}
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}
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}
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}
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}
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#[cfg(any(rtc_v3, rtc_v3u5))]
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crate::pac::RCC.bdcr().modify(|w| f(w))
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#[allow(dead_code)]
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fn unlock_registers() {
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// Unlock the backup domain
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#[cfg(not(any(rtc_v3u5, rcc_wl5, rcc_wle)))]
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{
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if !crate::pac::PWR.cr1().read().dbp() {
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crate::pac::PWR.cr1().modify(|w| w.set_dbp(true));
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while !crate::pac::PWR.cr1().read().dbp() {}
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}
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}
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#[cfg(any(rcc_wl5, rcc_wle))]
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{
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use crate::pac::pwr::vals::Dbp;
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if crate::pac::PWR.cr1().read().dbp() != Dbp::ENABLED {
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crate::pac::PWR.cr1().modify(|w| w.set_dbp(Dbp::ENABLED));
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while crate::pac::PWR.cr1().read().dbp() != Dbp::ENABLED {}
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}
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}
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}
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}
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#[cfg(any(
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#[cfg(any(
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rtc_v2f0, rtc_v2f2, rtc_v2f3, rtc_v2f4, rtc_v2f7, rtc_v2h7, rtc_v2l0, rtc_v2l1, rtc_v2l4, rtc_v2wb
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rtc_v2f0, rtc_v2f2, rtc_v2f3, rtc_v2f4, rtc_v2f7, rtc_v2h7, rtc_v2l0, rtc_v2l1, rtc_v2l4, rtc_v2wb, rtc_v3,
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rtc_v3u5
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))]
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#[allow(dead_code)]
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fn read() -> Bdcr {
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#[cfg(any(rtc_v2l0, rtc_v2l1))]
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let r = crate::pac::RCC.csr().read();
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#[cfg(not(any(rtc_v2l0, rtc_v2l1)))]
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let r = crate::pac::RCC.bdcr().read();
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r
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}
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#[cfg(any(
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rtc_v2f0, rtc_v2f2, rtc_v2f3, rtc_v2f4, rtc_v2f7, rtc_v2h7, rtc_v2l0, rtc_v2l1, rtc_v2l4, rtc_v2wb, rtc_v3,
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rtc_v3u5
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))]
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))]
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#[allow(dead_code)]
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#[allow(dead_code)]
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pub fn set_rtc_clock_source(clock_source: RtcClockSource) {
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#[cfg(not(rtc_v2wb))]
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use stm32_metapac::rcc::vals::Rtcsel;
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#[cfg(not(any(rtc_v2l0, rtc_v2l1)))]
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let cr = crate::pac::RCC.bdcr();
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#[cfg(any(rtc_v2l0, rtc_v2l1))]
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let cr = crate::pac::RCC.csr();
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Self::unlock_registers();
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cr.modify(|w| {
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// Select RTC source
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#[cfg(not(rtc_v2wb))]
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w.set_rtcsel(Rtcsel::from_bits(clock_source as u8));
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#[cfg(rtc_v2wb)]
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w.set_rtcsel(clock_source as u8);
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});
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}
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#[cfg(any(rtc_v3, rtc_v3u5))]
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#[allow(dead_code)]
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pub fn set_rtc_clock_source(clock_source: RtcClockSource) {
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pub fn set_rtc_clock_source(clock_source: RtcClockSource) {
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let clock_source = clock_source as u8;
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let clock_source = clock_source as u8;
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#[cfg(not(any(rcc_wl5, rcc_wle)))]
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#[cfg(any(
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all(not(any(rtc_v3, rtc_v3u5)), not(rtc_v2wb)),
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all(any(rtc_v3, rtc_v3u5), not(any(rcc_wl5, rcc_wle)))
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))]
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let clock_source = crate::pac::rcc::vals::Rtcsel::from_bits(clock_source);
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let clock_source = crate::pac::rcc::vals::Rtcsel::from_bits(clock_source);
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Self::unlock_registers();
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#[cfg(not(rtc_v2wb))]
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Self::modify(|w| {
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crate::pac::RCC.bdcr().modify(|w| {
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// Select RTC source
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// Select RTC source
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w.set_rtcsel(clock_source);
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w.set_rtcsel(clock_source);
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});
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});
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@ -102,25 +83,16 @@ impl BackupDomain {
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))]
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))]
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#[allow(dead_code)]
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#[allow(dead_code)]
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pub fn enable_rtc() {
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pub fn enable_rtc() {
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#[cfg(not(any(rtc_v2l0, rtc_v2l1)))]
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let reg = Self::read();
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let reg = crate::pac::RCC.bdcr().read();
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#[cfg(any(rtc_v2l0, rtc_v2l1))]
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let reg = crate::pac::RCC.csr().read();
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#[cfg(any(rtc_v2h7, rtc_v2l4, rtc_v2wb))]
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#[cfg(any(rtc_v2h7, rtc_v2l4, rtc_v2wb))]
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assert!(!reg.lsecsson(), "RTC is not compatible with LSE CSS, yet.");
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assert!(!reg.lsecsson(), "RTC is not compatible with LSE CSS, yet.");
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if !reg.rtcen() {
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if !reg.rtcen() {
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Self::unlock_registers();
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#[cfg(not(any(rtc_v2l0, rtc_v2l1, rtc_v2f2)))]
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#[cfg(not(any(rtc_v2l0, rtc_v2l1, rtc_v2f2)))]
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crate::pac::RCC.bdcr().modify(|w| w.set_bdrst(true));
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Self::modify(|w| w.set_bdrst(true));
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#[cfg(not(any(rtc_v2l0, rtc_v2l1)))]
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let cr = crate::pac::RCC.bdcr();
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#[cfg(any(rtc_v2l0, rtc_v2l1))]
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let cr = crate::pac::RCC.csr();
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cr.modify(|w| {
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Self::modify(|w| {
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// Reset
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// Reset
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#[cfg(not(any(rtc_v2l0, rtc_v2l1)))]
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#[cfg(not(any(rtc_v2l0, rtc_v2l1)))]
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w.set_bdrst(false);
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w.set_bdrst(false);
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@ -146,18 +118,13 @@ impl BackupDomain {
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#[cfg(any(rtc_v3, rtc_v3u5))]
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#[cfg(any(rtc_v3, rtc_v3u5))]
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#[allow(dead_code)]
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#[allow(dead_code)]
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pub fn enable_rtc() {
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pub fn enable_rtc() {
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let bdcr = crate::pac::RCC.bdcr();
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let reg = Self::read();
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let reg = bdcr.read();
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assert!(!reg.lsecsson(), "RTC is not compatible with LSE CSS, yet.");
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assert!(!reg.lsecsson(), "RTC is not compatible with LSE CSS, yet.");
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if !reg.rtcen() {
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if !reg.rtcen() {
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Self::unlock_registers();
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Self::modify(|w| w.set_bdrst(true));
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bdcr.modify(|w| w.set_bdrst(true));
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Self::modify(|w| {
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bdcr.modify(|w| {
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// Reset
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w.set_bdrst(false);
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w.set_bdrst(false);
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w.set_rtcen(true);
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w.set_rtcen(true);
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@ -1,5 +1,4 @@
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pub use super::bus::{AHBPrescaler, APBPrescaler, VoltageScale};
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pub use super::bus::{AHBPrescaler, APBPrescaler, VoltageScale};
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use crate::pac::pwr::vals::Dbp;
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use crate::pac::{FLASH, PWR, RCC};
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use crate::pac::{FLASH, PWR, RCC};
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use crate::rcc::bd::{BackupDomain, RtcClockSource};
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use crate::rcc::bd::{BackupDomain, RtcClockSource};
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use crate::rcc::{set_freqs, Clocks};
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use crate::rcc::{set_freqs, Clocks};
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@ -212,7 +211,7 @@ pub(crate) unsafe fn init(config: Config) {
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match config.rtc_mux {
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match config.rtc_mux {
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RtcClockSource::LSE => {
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RtcClockSource::LSE => {
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// 1. Unlock the backup domain
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// 1. Unlock the backup domain
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PWR.cr1().modify(|w| w.set_dbp(Dbp::ENABLED));
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PWR.cr1().modify(|w| w.set_dbp(true));
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// 2. Setup the LSE
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// 2. Setup the LSE
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RCC.bdcr().modify(|w| {
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RCC.bdcr().modify(|w| {
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