Refactor DMA implementation of I2C v1, clarify flow of code
This commit is contained in:
Sebastian Goll
parent
7e44db099c
commit
54d7d49513
1 changed files with 73 additions and 58 deletions
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@ -142,7 +142,7 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
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return Err(Error::Arbitration);
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}
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// Set up current address, we're trying to talk to
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// Set up current address we're trying to talk to
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T::regs().dr().write(|reg| reg.set_dr(addr << 1));
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// Wait until address was sent
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@ -235,7 +235,7 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
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return Err(Error::Arbitration);
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}
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// Set up current address, we're trying to talk to
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// Set up current address we're trying to talk to
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T::regs().dr().write(|reg| reg.set_dr((addr << 1) + 1));
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// Wait until address was sent
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@ -331,27 +331,21 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
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where
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TXDMA: crate::i2c::TxDma<T>,
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{
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let dma_transfer = unsafe {
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let regs = T::regs();
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regs.cr2().modify(|w| {
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// Note: Do not enable the ITBUFEN bit in the I2C_CR2 register if DMA is used for reception.
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w.set_itbufen(false);
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// DMA mode can be enabled for transmission by setting the DMAEN bit in the I2C_CR2 register.
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w.set_dmaen(true);
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// Sending NACK is not necessary (nor possible) for write transfer.
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w.set_last(false);
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});
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// Set the I2C_DR register address in the DMA_SxPAR register. The data will be moved to this address from the memory after each TxE event.
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let dst = regs.dr().as_ptr() as *mut u8;
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let ch = &mut self.tx_dma;
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let request = ch.request();
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Transfer::new_write(ch, request, write, dst, Default::default())
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};
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T::regs().cr2().modify(|w| {
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// Note: Do not enable the ITBUFEN bit in the I2C_CR2 register if DMA is used for
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// reception.
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w.set_itbufen(false);
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// DMA mode can be enabled for transmission by setting the DMAEN bit in the I2C_CR2
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// register.
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w.set_dmaen(true);
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// Sending NACK is not necessary (nor possible) for write transfer.
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w.set_last(false);
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});
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// Sentinel to disable transfer when an error occurs or future is canceled.
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// TODO: Generate STOP condition on cancel?
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let on_drop = OnDrop::new(|| {
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let regs = T::regs();
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regs.cr2().modify(|w| {
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T::regs().cr2().modify(|w| {
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w.set_dmaen(false);
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w.set_iterren(false);
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w.set_itevten(false);
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@ -390,7 +384,7 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
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return Err(Error::Arbitration);
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}
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// Set up current address, we're trying to talk to
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// Set up current address we're trying to talk to
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T::regs().dr().write(|reg| reg.set_dr(address << 1));
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// Wait for the address to be acknowledged
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@ -416,14 +410,22 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
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T::regs().sr2().read();
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}
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let dma_transfer = unsafe {
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// Set the I2C_DR register address in the DMA_SxPAR register. The data will be moved to
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// this address from the memory after each TxE event.
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let dst = T::regs().dr().as_ptr() as *mut u8;
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let ch = &mut self.tx_dma;
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let request = ch.request();
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Transfer::new_write(ch, request, write, dst, Default::default())
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};
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// Wait for bytes to be sent, or an error to occur.
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let poll_error = poll_fn(|cx| {
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state.waker.register(cx.waker());
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match Self::check_and_clear_error_flags() {
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// Unclear why the Err turbofish is necessary here? The compiler didn’t require it in the other
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// identical poll_fn check_and_clear matches.
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Err(e) => Poll::Ready(Err::<T, Error>(e)),
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Err(e) => Poll::Ready(Err::<(), Error>(e)),
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Ok(_) => {
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// When pending, (re-)enable interrupts to wake us up.
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Self::enable_interrupts();
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@ -502,31 +504,30 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
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where
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RXDMA: crate::i2c::RxDma<T>,
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{
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let buffer_len = buffer.len();
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if buffer.is_empty() {
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return Err(Error::Overrun);
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}
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let dma_transfer = unsafe {
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let regs = T::regs();
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regs.cr2().modify(|w| {
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// Note: Do not enable the ITBUFEN bit in the I2C_CR2 register if DMA is used for reception.
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w.set_itbufen(false);
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// DMA mode can be enabled for transmission by setting the DMAEN bit in the I2C_CR2 register.
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w.set_dmaen(true);
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// If, in the I2C_CR2 register, the LAST bit is set, I2C
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// automatically sends a NACK after the next byte following EOT_1. The user can
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// generate a Stop condition in the DMA Transfer Complete interrupt routine if enabled.
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w.set_last(frame.send_nack() && buffer_len != 1);
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});
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// Set the I2C_DR register address in the DMA_SxPAR register. The data will be moved to this address from the memory after each TxE event.
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let src = regs.dr().as_ptr() as *mut u8;
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// Some branches below depend on whether the buffer contains only a single byte.
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let single_byte = buffer.len() == 1;
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let ch = &mut self.rx_dma;
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let request = ch.request();
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Transfer::new_read(ch, request, src, buffer, Default::default())
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};
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T::regs().cr2().modify(|w| {
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// Note: Do not enable the ITBUFEN bit in the I2C_CR2 register if DMA is used for
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// reception.
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w.set_itbufen(false);
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// DMA mode can be enabled for transmission by setting the DMAEN bit in the I2C_CR2
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// register.
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w.set_dmaen(true);
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// If, in the I2C_CR2 register, the LAST bit is set, I2C automatically sends a NACK
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// after the next byte following EOT_1. The user can generate a Stop condition in
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// the DMA Transfer Complete interrupt routine if enabled.
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w.set_last(frame.send_nack() && !single_byte);
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});
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// Sentinel to disable transfer when an error occurs or future is canceled.
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// TODO: Generate STOP condition on cancel?
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let on_drop = OnDrop::new(|| {
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let regs = T::regs();
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regs.cr2().modify(|w| {
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T::regs().cr2().modify(|w| {
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w.set_dmaen(false);
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w.set_iterren(false);
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w.set_itevten(false);
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@ -566,7 +567,7 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
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return Err(Error::Arbitration);
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}
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// Set up current address, we're trying to talk to
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// Set up current address we're trying to talk to
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T::regs().dr().write(|reg| reg.set_dr((address << 1) + 1));
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// Wait for the address to be acknowledged
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@ -590,7 +591,7 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
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// 18.3.8: When a single byte must be received: the NACK must be programmed during EV6
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// event, i.e. program ACK=0 when ADDR=1, before clearing ADDR flag.
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if frame.send_nack() && buffer_len == 1 {
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if frame.send_nack() && single_byte {
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T::regs().cr1().modify(|w| {
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w.set_ack(false);
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});
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@ -598,27 +599,41 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
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// Clear condition by reading SR2
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T::regs().sr2().read();
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} else if frame.send_nack() && buffer_len == 1 {
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T::regs().cr1().modify(|w| {
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w.set_ack(false);
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});
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} else {
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// Before starting reception of single byte (but without START condition, i.e. in case
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// of continued frame), program NACK to emit at end of this byte.
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if frame.send_nack() && single_byte {
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T::regs().cr1().modify(|w| {
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w.set_ack(false);
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});
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}
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}
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// 18.3.8: When a single byte must be received: [snip] Then the
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// user can program the STOP condition either after clearing ADDR flag, or in the
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// DMA Transfer Complete interrupt routine.
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if frame.send_stop() && buffer_len == 1 {
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// 18.3.8: When a single byte must be received: [snip] Then the user can program the STOP
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// condition either after clearing ADDR flag, or in the DMA Transfer Complete interrupt
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// routine.
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if frame.send_stop() && single_byte {
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T::regs().cr1().modify(|w| {
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w.set_stop(true);
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});
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}
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let dma_transfer = unsafe {
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// Set the I2C_DR register address in the DMA_SxPAR register. The data will be moved
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// from this address from the memory after each RxE event.
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let src = T::regs().dr().as_ptr() as *mut u8;
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let ch = &mut self.rx_dma;
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let request = ch.request();
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Transfer::new_read(ch, request, src, buffer, Default::default())
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};
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// Wait for bytes to be received, or an error to occur.
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let poll_error = poll_fn(|cx| {
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state.waker.register(cx.waker());
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match Self::check_and_clear_error_flags() {
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Err(e) => Poll::Ready(Err::<T, Error>(e)),
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Err(e) => Poll::Ready(Err::<(), Error>(e)),
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_ => {
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// When pending, (re-)enable interrupts to wake us up.
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Self::enable_interrupts();
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@ -636,7 +651,7 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
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w.set_dmaen(false);
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});
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if frame.send_stop() && buffer_len != 1 {
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if frame.send_stop() && !single_byte {
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T::regs().cr1().modify(|w| {
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w.set_stop(true);
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});
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