NaxdyOrg/embassy
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity

feature-gate set_channel_mode, undo dma.rs changes

Browse source
This commit is contained in:
JuliDi 2023-06-27 21:23:47 +02:00
parent afec1b439b
commit 56dd22f0ac
No known key found for this signature in database
GPG key ID: E1E90AE563D09D63
2 changed files with 11 additions and 24 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

17
embassy-stm32/src/dac/mod.rs
View file

@ -127,6 +127,7 @@ pub trait DacChannel<T: Instance, Tx> {
} }
/// Set mode register of the given channel /// Set mode register of the given channel
#[cfg(dac_v2)]
fn set_channel_mode(&mut self, val: u8) -> Result<(), Error> { fn set_channel_mode(&mut self, val: u8) -> Result<(), Error> {
T::regs().mcr().modify(|reg| { T::regs().mcr().modify(|reg| {
reg.set_mode(Self::CHANNEL.index(), val); reg.set_mode(Self::CHANNEL.index(), val);
@ -221,6 +222,7 @@ impl<'d, T: Instance, Tx> DacCh1<'d, T, Tx> {
// Configure each activated channel. All results can be `unwrap`ed since they // Configure each activated channel. All results can be `unwrap`ed since they
// will only error if the channel is not configured (i.e. ch1, ch2 are false) // will only error if the channel is not configured (i.e. ch1, ch2 are false)
#[cfg(dac_v2)]
dac.set_channel_mode(0).unwrap(); dac.set_channel_mode(0).unwrap();
dac.enable_channel().unwrap(); dac.enable_channel().unwrap();
dac.set_trigger_enable(true).unwrap(); dac.set_trigger_enable(true).unwrap();
@ -334,6 +336,7 @@ impl<'d, T: Instance, Tx> DacCh2<'d, T, Tx> {
// Configure each activated channel. All results can be `unwrap`ed since they // Configure each activated channel. All results can be `unwrap`ed since they
// will only error if the channel is not configured (i.e. ch1, ch2 are false) // will only error if the channel is not configured (i.e. ch1, ch2 are false)
#[cfg(dac_v2)]
dac.set_channel_mode(0).unwrap(); dac.set_channel_mode(0).unwrap();
dac.enable_channel().unwrap(); dac.enable_channel().unwrap();
dac.set_trigger_enable(true).unwrap(); dac.set_trigger_enable(true).unwrap();
@ -454,10 +457,12 @@ impl<'d, T: Instance, TxCh1, TxCh2> Dac<'d, T, TxCh1, TxCh2> {
// Configure each activated channel. All results can be `unwrap`ed since they // Configure each activated channel. All results can be `unwrap`ed since they
// will only error if the channel is not configured (i.e. ch1, ch2 are false) // will only error if the channel is not configured (i.e. ch1, ch2 are false)
#[cfg(dac_v2)]
dac_ch1.set_channel_mode(0).unwrap(); dac_ch1.set_channel_mode(0).unwrap();
dac_ch1.enable_channel().unwrap(); dac_ch1.enable_channel().unwrap();
dac_ch1.set_trigger_enable(true).unwrap(); dac_ch1.set_trigger_enable(true).unwrap();
#[cfg(dac_v2)]
dac_ch2.set_channel_mode(0).unwrap(); dac_ch2.set_channel_mode(0).unwrap();
dac_ch2.enable_channel().unwrap(); dac_ch2.enable_channel().unwrap();
dac_ch2.set_trigger_enable(true).unwrap(); dac_ch2.set_trigger_enable(true).unwrap();
@ -521,27 +526,25 @@ foreach_peripheral!(
#[cfg(rcc_h7)] #[cfg(rcc_h7)]
impl crate::rcc::sealed::RccPeripheral for peripherals::$inst { impl crate::rcc::sealed::RccPeripheral for peripherals::$inst {
fn frequency() -> crate::time::Hertz { fn frequency() -> crate::time::Hertz {
critical_section::with(|_| unsafe { critical_section::with(|_| crate::rcc::get_freqs().apb1)
crate::rcc::get_freqs().apb1
})
} }
fn reset() { fn reset() {
critical_section::with(|_| unsafe { critical_section::with(|_| {
crate::pac::RCC.apb1lrstr().modify(|w| w.set_dac12rst(true)); crate::pac::RCC.apb1lrstr().modify(|w| w.set_dac12rst(true));
crate::pac::RCC.apb1lrstr().modify(|w| w.set_dac12rst(false)); crate::pac::RCC.apb1lrstr().modify(|w| w.set_dac12rst(false));
}) })
} }
fn enable() { fn enable() {
critical_section::with(|_| unsafe { critical_section::with(|_| {
crate::pac::RCC.apb1lenr().modify(|w| w.set_dac12en(true)); crate::pac::RCC.apb1lenr().modify(|w| w.set_dac12en(true));
}) })
} }
fn disable() { fn disable() {
critical_section::with(|_| unsafe { critical_section::with(|_| {
crate::pac::RCC.apb1lenr().modify(|w| w.set_dac12en(false)); crate::pac::RCC.apb1lenr().modify(|w| w.set_dac12en(false))
}) })
} }
} }

18
embassy-stm32/src/dma/dma.rs
View file

@ -29,12 +29,6 @@ pub struct TransferOptions {
pub flow_ctrl: FlowControl, pub flow_ctrl: FlowControl,
/// FIFO threshold for DMA FIFO mode. If none, direct mode is used. /// FIFO threshold for DMA FIFO mode. If none, direct mode is used.
pub fifo_threshold: Option<FifoThreshold>, pub fifo_threshold: Option<FifoThreshold>,
/// Enable circular DMA
pub circular: bool,
/// Enable half transfer interrupt
pub half_transfer_ir: bool,
/// Enable transfer complete interrupt
pub complete_transfer_ir: bool,
} }
impl Default for TransferOptions { impl Default for TransferOptions {
@ -44,9 +38,6 @@ impl Default for TransferOptions {
mburst: Burst::Single, mburst: Burst::Single,
flow_ctrl: FlowControl::Dma, flow_ctrl: FlowControl::Dma,
fifo_threshold: None, fifo_threshold: None,
circular: false,
half_transfer_ir: false,
complete_transfer_ir: true,
} }
} }
} }
@ -375,20 +366,13 @@ impl<'a, C: Channel> Transfer<'a, C> {
}); });
w.set_pinc(vals::Inc::FIXED); w.set_pinc(vals::Inc::FIXED);
w.set_teie(true); w.set_teie(true);
w.set_tcie(options.complete_transfer_ir); w.set_tcie(true);
w.set_htie(options.half_transfer_ir);
#[cfg(dma_v1)] #[cfg(dma_v1)]
w.set_trbuff(true); w.set_trbuff(true);
#[cfg(dma_v2)] #[cfg(dma_v2)]
w.set_chsel(_request); w.set_chsel(_request);
if options.circular {
w.set_circ(vals::Circ::ENABLED);
debug!("Setting circular mode");
} else {
w.set_circ(vals::Circ::DISABLED);
}
w.set_pburst(options.pburst.into()); w.set_pburst(options.pburst.into());
w.set_mburst(options.mburst.into()); w.set_mburst(options.mburst.into());
w.set_pfctrl(options.flow_ctrl.into()); w.set_pfctrl(options.flow_ctrl.into());