stm32: add initial rcc mux for h5
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xoviat
parent
ac84631a2a
commit
57ccc1051a
3 changed files with 202 additions and 10 deletions
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@ -5,7 +5,8 @@ use std::{env, fs};
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use proc_macro2::{Ident, TokenStream};
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use quote::{format_ident, quote};
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use stm32_metapac::metadata::{MemoryRegionKind, METADATA};
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use stm32_metapac::metadata::ir::{BlockItemInner, Enum};
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use stm32_metapac::metadata::{MemoryRegionKind, PeripheralRccRegister, METADATA};
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fn main() {
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let target = env::var("TARGET").unwrap();
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@ -387,6 +388,51 @@ fn main() {
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});
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}
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// ========
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// Generate rcc fieldset and enum maps
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let rcc_enum_map: HashMap<&str, HashMap<&str, &Enum>> = {
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let rcc_registers = METADATA
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.peripherals
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.iter()
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.filter_map(|p| p.registers.as_ref())
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.find(|r| r.kind == "rcc")
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.unwrap()
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.ir;
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let rcc_blocks = rcc_registers.blocks.iter().find(|b| b.name == "Rcc").unwrap().items;
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let rcc_block_item_map: HashMap<&str, &str> = rcc_blocks
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.iter()
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.filter_map(|b| match &b.inner {
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BlockItemInner::Register(register) => register.fieldset.map(|f| (f, b.name)),
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_ => None,
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})
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.collect();
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let rcc_enum_map: HashMap<&str, &Enum> = rcc_registers.enums.iter().map(|e| (e.name, e)).collect();
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rcc_registers
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.fieldsets
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.iter()
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.filter_map(|f| {
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rcc_block_item_map.get(f.name).map(|b| {
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(
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*b,
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f.fields
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.iter()
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.filter_map(|f| {
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let enumm = f.enumm?;
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let enumm = rcc_enum_map.get(enumm)?;
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Some((f.name, *enumm))
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})
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.collect(),
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)
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})
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})
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.collect()
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};
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// ========
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// Generate RccPeripheral impls
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@ -454,10 +500,61 @@ fn main() {
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(TokenStream::new(), TokenStream::new())
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};
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let mux_for = |mux: Option<&'static PeripheralRccRegister>| {
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// temporary hack to restrict the scope of the implementation to h5
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if !&chip_name.starts_with("stm32h5") {
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return None;
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}
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let mux = mux?;
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let fieldset = rcc_enum_map.get(mux.register)?;
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let enumm = fieldset.get(mux.field)?;
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Some((mux, *enumm))
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};
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let clock_frequency = match mux_for(rcc.mux.as_ref()) {
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Some((mux, rcc_enumm)) => {
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let fieldset_name = format_ident!("{}", mux.register);
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let field_name = format_ident!("{}", mux.field);
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let enum_name = format_ident!("{}", rcc_enumm.name);
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let match_arms: TokenStream = rcc_enumm
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.variants
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.iter()
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.filter(|v| v.name != "DISABLE")
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.map(|v| {
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let variant_name = format_ident!("{}", v.name);
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// temporary hack to restrict the scope of the implementation until clock names can be stabilized
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let clock_name = format_ident!("mux_{}", v.name.to_ascii_lowercase());
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quote! {
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#enum_name::#variant_name => unsafe { crate::rcc::get_freqs().#clock_name.unwrap() },
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}
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})
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.collect();
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quote! {
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use crate::pac::rcc::vals::#enum_name;
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#[allow(unreachable_patterns)]
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match crate::pac::RCC.#fieldset_name().read().#field_name() {
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#match_arms
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_ => unreachable!(),
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}
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}
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}
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None => quote! {
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unsafe { crate::rcc::get_freqs().#clk }
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},
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};
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g.extend(quote! {
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impl crate::rcc::sealed::RccPeripheral for peripherals::#pname {
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fn frequency() -> crate::time::Hertz {
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unsafe { crate::rcc::get_freqs().#clk }
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#clock_frequency
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}
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fn enable() {
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critical_section::with(|_cs| {
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@ -486,12 +583,14 @@ fn main() {
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}
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}
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let mut refcount_mod = TokenStream::new();
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for refcount_static in refcount_statics {
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refcount_mod.extend(quote! {
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pub(crate) static mut #refcount_static: u8 = 0;
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});
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}
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let refcount_mod: TokenStream = refcount_statics
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.iter()
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.map(|refcount_static| {
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quote! {
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pub(crate) static mut #refcount_static: u8 = 0;
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}
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})
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.collect();
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g.extend(quote! {
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mod refcount_statics {
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@ -388,7 +388,7 @@ pub(crate) unsafe fn init(config: Config) {
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let pll1 = init_pll(0, config.pll1, &pll_input);
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let pll2 = init_pll(1, config.pll2, &pll_input);
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#[cfg(any(rcc_h5, stm32h7))]
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let _pll3 = init_pll(2, config.pll3, &pll_input);
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let pll3 = init_pll(2, config.pll3, &pll_input);
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// Configure sysclk
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let (sys, sw) = match config.sys {
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@ -447,7 +447,7 @@ pub(crate) unsafe fn init(config: Config) {
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#[cfg(stm32h7)]
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let adc = match config.adc_clock_source {
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AdcClockSource::PLL2_P => pll2.p,
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AdcClockSource::PLL3_R => _pll3.r,
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AdcClockSource::PLL3_R => pll3.r,
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AdcClockSource::PER => _per_ck,
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_ => unreachable!(),
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};
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@ -545,6 +545,53 @@ pub(crate) unsafe fn init(config: Config) {
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apb2_tim,
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adc,
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rtc,
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#[cfg(stm32h5)]
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mux_rcc_pclk1: Some(apb1),
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#[cfg(stm32h5)]
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mux_pll2_q: None,
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#[cfg(stm32h5)]
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mux_pll3_q: None,
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#[cfg(stm32h5)]
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mux_hsi_ker: None,
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#[cfg(stm32h5)]
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mux_csi_ker: None,
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#[cfg(stm32h5)]
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mux_lse: None,
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#[cfg(stm32h5)]
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mux_pll1_q: pll1.q,
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#[cfg(stm32h5)]
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mux_pll2_p: pll2.p,
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#[cfg(rcc_h5)]
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mux_pll3_p: pll3.p,
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#[cfg(stm32h5)]
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mux_audioclk: None,
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#[cfg(stm32h5)]
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mux_per: None,
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#[cfg(rcc_h5)]
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mux_pll3_r: pll3.r,
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#[cfg(all(not(rcc_h5), stm32h5))]
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mux_pll3_r: None,
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#[cfg(stm32h5)]
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mux_rcc_pclk3: Some(apb3),
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#[cfg(stm32h5)]
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mux_pll3_1: None,
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#[cfg(stm32h5)]
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mux_hsi48_ker: None,
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#[cfg(stm32h5)]
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mux_lsi_ker: None,
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#[cfg(stm32h5)]
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mux_pll2_r: pll2.r,
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#[cfg(stm32h5)]
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mux_rcc_pclk2: Some(apb2),
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#[cfg(stm32h5)]
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mux_rcc_pclk4: None,
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#[cfg(stm32h5)]
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mux_hse: hse,
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#[cfg(stm32h5)]
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mux_hsi48: None,
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});
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}
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@ -134,6 +134,52 @@ pub struct Clocks {
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pub hrtim: Option<Hertz>,
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pub rtc: Option<Hertz>,
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#[cfg(stm32h5)]
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pub mux_rcc_pclk1: Option<Hertz>,
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#[cfg(stm32h5)]
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pub mux_pll2_q: Option<Hertz>,
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#[cfg(stm32h5)]
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pub mux_pll3_q: Option<Hertz>,
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#[cfg(stm32h5)]
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pub mux_hsi_ker: Option<Hertz>,
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#[cfg(stm32h5)]
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pub mux_csi_ker: Option<Hertz>,
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#[cfg(stm32h5)]
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pub mux_lse: Option<Hertz>,
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#[cfg(stm32h5)]
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pub mux_pll1_q: Option<Hertz>,
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#[cfg(stm32h5)]
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pub mux_pll2_p: Option<Hertz>,
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#[cfg(rcc_h5)]
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pub mux_pll3_p: Option<Hertz>,
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#[cfg(stm32h5)]
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pub mux_audioclk: Option<Hertz>,
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#[cfg(stm32h5)]
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pub mux_per: Option<Hertz>,
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#[cfg(stm32h5)]
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pub mux_pll3_r: Option<Hertz>,
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#[cfg(stm32h5)]
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pub mux_rcc_pclk3: Option<Hertz>,
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#[cfg(stm32h5)]
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pub mux_pll3_1: Option<Hertz>,
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#[cfg(stm32h5)]
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pub mux_hsi48_ker: Option<Hertz>,
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#[cfg(stm32h5)]
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pub mux_lsi_ker: Option<Hertz>,
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#[cfg(stm32h5)]
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pub mux_pll2_r: Option<Hertz>,
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#[cfg(stm32h5)]
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pub mux_rcc_pclk2: Option<Hertz>,
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#[cfg(stm32h5)]
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pub mux_rcc_pclk4: Option<Hertz>,
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#[cfg(stm32h5)]
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pub mux_hse: Option<Hertz>,
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#[cfg(stm32h5)]
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pub mux_hsi48: Option<Hertz>,
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}
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#[cfg(feature = "low-power")]
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