stm32: add dac fix
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@ -51,7 +51,10 @@ impl Ch1Trigger {
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fn tsel(&self) -> dac::vals::Tsel1 {
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match self {
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Ch1Trigger::Tim6 => dac::vals::Tsel1::TIM6_TRGO,
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#[cfg(not(dac_v3))]
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Ch1Trigger::Tim3 => dac::vals::Tsel1::TIM3_TRGO,
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#[cfg(dac_v3)]
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Ch1Trigger::Tim3 => dac::vals::Tsel1::TIM1_TRGO,
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Ch1Trigger::Tim7 => dac::vals::Tsel1::TIM7_TRGO,
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Ch1Trigger::Tim15 => dac::vals::Tsel1::TIM15_TRGO,
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Ch1Trigger::Tim2 => dac::vals::Tsel1::TIM2_TRGO,
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