HIL test for STM32 FDCAN support.
Internal loopback. fdcan: use common.rs for HIL test. Fix tests. Fix tests. Fix tests Add HIL tests for H7 even though they are a bit crippled. CI fixes Bah Test bah
This commit is contained in:
Corey Schuhen
Corey Schuhen
parent
1698f4dbc3
commit
6e1047395d
2 changed files with 254 additions and 5 deletions
tests/stm32
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@ -14,11 +14,11 @@ stm32f429zi = ["embassy-stm32/stm32f429zi", "chrono", "eth", "stop", "can", "not
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stm32f446re = ["embassy-stm32/stm32f446re", "chrono", "stop", "can", "not-gpdma", "dac", "sdmmc"]
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stm32f767zi = ["embassy-stm32/stm32f767zi", "chrono", "not-gpdma", "eth", "rng"]
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stm32g071rb = ["embassy-stm32/stm32g071rb", "cm0", "not-gpdma", "dac"]
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stm32g491re = ["embassy-stm32/stm32g491re", "chrono", "stop", "not-gpdma", "rng"]
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stm32h563zi = ["embassy-stm32/stm32h563zi", "chrono", "eth", "rng"]
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stm32h753zi = ["embassy-stm32/stm32h753zi", "chrono", "not-gpdma", "eth", "rng"]
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stm32h755zi = ["embassy-stm32/stm32h755zi-cm7", "chrono", "not-gpdma", "eth", "dac", "rng"]
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stm32h7a3zi = ["embassy-stm32/stm32h7a3zi", "not-gpdma", "rng"]
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stm32g491re = ["embassy-stm32/stm32g491re", "chrono", "stop", "not-gpdma", "rng", "fdcan"]
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stm32h563zi = ["embassy-stm32/stm32h563zi", "chrono", "eth", "rng", "fdcan"]
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stm32h753zi = ["embassy-stm32/stm32h753zi", "chrono", "not-gpdma", "eth", "rng", "fdcan"]
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stm32h755zi = ["embassy-stm32/stm32h755zi-cm7", "chrono", "not-gpdma", "eth", "dac", "rng", "fdcan"]
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stm32h7a3zi = ["embassy-stm32/stm32h7a3zi", "not-gpdma", "rng", "fdcan"]
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stm32l073rz = ["embassy-stm32/stm32l073rz", "cm0", "not-gpdma", "rng"]
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stm32l152re = ["embassy-stm32/stm32l152re", "chrono", "not-gpdma"]
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stm32l496zg = ["embassy-stm32/stm32l496zg", "not-gpdma", "rng"]
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@ -37,6 +37,7 @@ sdmmc = []
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stop = ["embassy-stm32/low-power", "embassy-stm32/low-power-debug-with-sleep"]
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chrono = ["embassy-stm32/chrono", "dep:chrono"]
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can = []
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fdcan = []
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ble = ["dep:embassy-stm32-wpan", "embassy-stm32-wpan/ble"]
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mac = ["dep:embassy-stm32-wpan", "embassy-stm32-wpan/mac"]
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embassy-stm32-wpan = []
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@ -96,6 +97,11 @@ name = "eth"
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path = "src/bin/eth.rs"
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required-features = [ "eth",]
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[[bin]]
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name = "fdcan"
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path = "src/bin/fdcan.rs"
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required-features = [ "fdcan",]
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[[bin]]
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name = "gpio"
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path = "src/bin/gpio.rs"
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243
tests/stm32/src/bin/fdcan.rs
Normal file
243
tests/stm32/src/bin/fdcan.rs
Normal file
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@ -0,0 +1,243 @@
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#![no_std]
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#![no_main]
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// required-features: fdcan
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#[path = "../common.rs"]
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mod common;
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use common::*;
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use defmt::assert;
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use embassy_executor::Spawner;
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use embassy_stm32::peripherals::*;
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use embassy_stm32::{bind_interrupts, can, Config};
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use embassy_time::{Duration, Instant};
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use {defmt_rtt as _, panic_probe as _};
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bind_interrupts!(struct Irqs {
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FDCAN1_IT0 => can::IT0InterruptHandler<FDCAN1>;
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FDCAN1_IT1 => can::IT1InterruptHandler<FDCAN1>;
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});
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struct TestOptions {
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config: Config,
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max_latency: Duration,
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second_fifo_working: bool,
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}
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#[cfg(any(feature = "stm32h755zi", feature = "stm32h753zi", feature = "stm32h563zi"))]
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fn options() -> TestOptions {
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use embassy_stm32::rcc;
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info!("H75 config");
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let mut c = config();
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c.rcc.hse = Some(rcc::Hse {
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freq: embassy_stm32::time::Hertz(25_000_000),
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mode: rcc::HseMode::Oscillator,
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});
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c.rcc.fdcan_clock_source = rcc::FdCanClockSource::HSE;
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TestOptions {
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config: c,
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max_latency: Duration::from_micros(3800),
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second_fifo_working: false,
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}
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}
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#[cfg(any(feature = "stm32h7a3zi"))]
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fn options() -> TestOptions {
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use embassy_stm32::rcc;
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info!("H7a config");
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let mut c = config();
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c.rcc.hse = Some(rcc::Hse {
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freq: embassy_stm32::time::Hertz(25_000_000),
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mode: rcc::HseMode::Oscillator,
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});
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c.rcc.fdcan_clock_source = rcc::FdCanClockSource::HSE;
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TestOptions {
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config: c,
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max_latency: Duration::from_micros(5500),
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second_fifo_working: false,
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}
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}
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#[cfg(any(feature = "stm32g491re"))]
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fn options() -> TestOptions {
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info!("G4 config");
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TestOptions {
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config: config(),
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max_latency: Duration::from_micros(500),
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second_fifo_working: true,
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}
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}
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#[embassy_executor::main]
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async fn main(_spawner: Spawner) {
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//let peripherals = embassy_stm32::init(config());
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let options = options();
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let peripherals = embassy_stm32::init(options.config);
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let mut can = can::Fdcan::new(peripherals.FDCAN1, peripherals.PB8, peripherals.PB9, Irqs);
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// 250k bps
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can.set_bitrate(250_000);
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can.can.set_extended_filter(
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can::filter::ExtendedFilterSlot::_0,
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can::filter::ExtendedFilter::accept_all_into_fifo1(),
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);
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let mut can = can.into_internal_loopback_mode();
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info!("CAN Configured");
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let mut i: u8 = 0;
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loop {
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let tx_frame = can::TxFrame::new(
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can::TxFrameHeader {
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len: 1,
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frame_format: can::FrameFormat::Standard,
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id: can::StandardId::new(0x123).unwrap().into(),
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bit_rate_switching: false,
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marker: None,
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},
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&[i],
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)
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.unwrap();
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info!("Transmitting frame...");
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let tx_ts = Instant::now();
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can.write(&tx_frame).await;
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let envelope = can.read().await.unwrap();
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info!("Frame received!");
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// Check data.
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assert!(i == envelope.data()[0], "{} == {}", i, envelope.data()[0]);
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info!("loopback time {}", envelope.header.time_stamp);
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info!("loopback frame {=u8}", envelope.data()[0]);
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let latency = envelope.timestamp.saturating_duration_since(tx_ts);
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info!("loopback latency {} us", latency.as_micros());
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// Theoretical minimum latency is 55us, actual is usually ~80us
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const MIN_LATENCY: Duration = Duration::from_micros(50);
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// Was failing at 150 but we are not getting a real time stamp. I'm not
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// sure if there are other delays
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assert!(
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MIN_LATENCY <= latency && latency <= options.max_latency,
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"{} <= {} <= {}",
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MIN_LATENCY,
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latency,
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options.max_latency
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);
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i += 1;
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if i > 10 {
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break;
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}
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}
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let max_buffered = if options.second_fifo_working { 6 } else { 3 };
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// Below here, check that we can receive from both FIFO0 and FIFO0
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// Above we configured FIFO1 for extended ID packets. There are only 3 slots
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// in each FIFO so make sure we write enough to fill them both up before reading.
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for i in 0..3 {
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// Try filling up the RX FIFO0 buffers with standard packets
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let tx_frame = can::TxFrame::new(
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can::TxFrameHeader {
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len: 1,
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frame_format: can::FrameFormat::Standard,
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id: can::StandardId::new(0x123).unwrap().into(),
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bit_rate_switching: false,
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marker: None,
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},
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&[i],
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)
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.unwrap();
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info!("Transmitting frame {}", i);
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can.write(&tx_frame).await;
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}
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for i in 3..max_buffered {
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// Try filling up the RX FIFO0 buffers with extended packets
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let tx_frame = can::TxFrame::new(
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can::TxFrameHeader {
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len: 1,
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frame_format: can::FrameFormat::Standard,
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id: can::ExtendedId::new(0x1232344).unwrap().into(),
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bit_rate_switching: false,
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marker: None,
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},
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&[i],
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)
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.unwrap();
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info!("Transmitting frame {}", i);
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can.write(&tx_frame).await;
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}
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// Try and receive all 6 packets
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for i in 0..max_buffered {
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let envelope = can.read().await.unwrap();
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match envelope.header.id {
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can::Id::Extended(id) => {
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info!("Extended received! {:x} {} {}", id.as_raw(), envelope.data()[0], i);
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}
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can::Id::Standard(id) => {
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info!("Standard received! {:x} {} {}", id.as_raw(), envelope.data()[0], i);
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}
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}
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}
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// Test again with a split
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let (mut tx, mut rx) = can.split();
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for i in 0..3 {
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// Try filling up the RX FIFO0 buffers with standard packets
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let tx_frame = can::TxFrame::new(
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can::TxFrameHeader {
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len: 1,
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frame_format: can::FrameFormat::Standard,
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id: can::StandardId::new(0x123).unwrap().into(),
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bit_rate_switching: false,
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marker: None,
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},
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&[i],
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)
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.unwrap();
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info!("Transmitting frame {}", i);
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tx.write(&tx_frame).await;
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}
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for i in 3..max_buffered {
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// Try filling up the RX FIFO0 buffers with extended packets
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let tx_frame = can::TxFrame::new(
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can::TxFrameHeader {
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len: 1,
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frame_format: can::FrameFormat::Standard,
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id: can::ExtendedId::new(0x1232344).unwrap().into(),
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bit_rate_switching: false,
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marker: None,
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},
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&[i],
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)
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.unwrap();
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info!("Transmitting frame {}", i);
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tx.write(&tx_frame).await;
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}
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// Try and receive all 6 packets
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for i in 0..max_buffered {
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let envelope = rx.read().await.unwrap();
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match envelope.header.id {
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can::Id::Extended(id) => {
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info!("Extended received! {:x} {} {}", id.as_raw(), envelope.data()[0], i);
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}
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can::Id::Standard(id) => {
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info!("Standard received! {:x} {} {}", id.as_raw(), envelope.data()[0], i);
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}
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}
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}
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info!("Test OK");
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cortex_m::asm::bkpt();
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}
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