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[UCPD] Adjust TX clock divider

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This commit is contained in:
Timo Kröger 2024-03-12 20:40:00 +01:00
parent e95e95ac7a
commit 6e5bb8003a
1 changed files with 2 additions and 4 deletions

6
embassy-stm32/src/ucpd.rs
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@ -112,10 +112,8 @@ impl<'d, T: Instance> Ucpd<'d, T> {
// Prescaler to produce a target half-bit frequency of 600kHz which is required // Prescaler to produce a target half-bit frequency of 600kHz which is required
// to produce transmit with a nominal nominal bit rate of 300Kbps+-10% using // to produce transmit with a nominal nominal bit rate of 300Kbps+-10% using
// biphase mark coding (BMC, aka differential manchester coding). // biphase mark coding (BMC, aka differential manchester coding).
// A divider of 13 gives the target frequency closest to spec (~615kHz, 1.625us) // A divider of 13 gives the target frequency closest to spec (~615kHz, 1.625us).
// but we go with the (hopefully well tested) default value used by the Cube HAL w.set_hbitclkdiv(13 - 1);
// which is 14 divides the clock down to ~571kHz, 1.75us.
w.set_hbitclkdiv(14 - 1);
// Time window for detecting non-idle (12-20us). // Time window for detecting non-idle (12-20us).
// 1.75us * 8 = 14us. // 1.75us * 8 = 14us.