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Update u5.rs

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Update comments on p and q divider values to correctly describe what the clock outputs are used for.
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Tyler 2024-01-03 11:04:48 -06:00 committed by GitHub
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commit 727906fa04
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1 changed files with 8 additions and 10 deletions
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18
embassy-stm32/src/rcc/u5.rs
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@ -45,17 +45,15 @@ pub struct PllConfig {
/// The multiplied clock – `source` divided by `m` times `n` – must be between 128 and 544 /// The multiplied clock – `source` divided by `m` times `n` – must be between 128 and 544
/// MHz. The upper limit may be lower depending on the `Config { voltage_range }`. /// MHz. The upper limit may be lower depending on the `Config { voltage_range }`.
pub n: Plln, pub n: Plln,
/// The divider for the P output. /// The divider for the P output.
/// ///
/// When used to drive the system clock, `source` divided by `m` times `n` divided by `r` /// The P output is one of several options
/// must not exceed 160 MHz. System clocks above 55 MHz require a non-default /// that can be used to feed the SAI/MDF/ADF Clock mux's.
/// `Config { voltage_range }`.
pub p: Plldiv, pub p: Plldiv,
/// The divider for the Q output. /// The divider for the Q output.
/// ///
/// When used to drive the system clock, `source` divided by `m` times `n` divided by `r` /// The Q ouput is one of severals options that can be used to feed the 48MHz clocks
/// must not exceed 160 MHz. System clocks above 55 MHz require a non-default /// and the OCTOSPI clock. It may also be used on the MDF/ADF clock mux's.
/// `Config { voltage_range }`.
pub q: Plldiv, pub q: Plldiv,
/// The divider for the R output. /// The divider for the R output.
/// ///