Merge pull request #1870 from plaes/nrf-setconfig-trait-internally
nrf: Use SetConfig trait internally where possible
This commit is contained in:
commit
77c357e744
4 changed files with 13 additions and 82 deletions
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@ -189,42 +189,10 @@ impl<'d, T: Instance> Spim<'d, T> {
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// Enable SPIM instance.
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// Enable SPIM instance.
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r.enable.write(|w| w.enable().enabled());
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r.enable.write(|w| w.enable().enabled());
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// Configure mode.
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let mut spim = Self { _p: spim };
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let mode = config.mode;
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r.config.write(|w| {
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match mode {
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MODE_0 => {
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w.order().msb_first();
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w.cpol().active_high();
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w.cpha().leading();
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}
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MODE_1 => {
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w.order().msb_first();
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w.cpol().active_high();
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w.cpha().trailing();
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}
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MODE_2 => {
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w.order().msb_first();
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w.cpol().active_low();
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w.cpha().leading();
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}
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MODE_3 => {
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w.order().msb_first();
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w.cpol().active_low();
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w.cpha().trailing();
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}
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}
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w
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// Apply runtime peripheral configuration
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});
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Self::set_config(&mut spim, &config);
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// Configure frequency.
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let frequency = config.frequency;
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r.frequency.write(|w| w.frequency().variant(frequency));
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// Set over-read character
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let orc = config.orc;
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r.orc.write(|w| unsafe { w.orc().bits(orc) });
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// Disable all events interrupts
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// Disable all events interrupts
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r.intenclr.write(|w| unsafe { w.bits(0xFFFF_FFFF) });
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r.intenclr.write(|w| unsafe { w.bits(0xFFFF_FFFF) });
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@ -232,7 +200,7 @@ impl<'d, T: Instance> Spim<'d, T> {
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T::Interrupt::unpend();
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T::Interrupt::unpend();
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unsafe { T::Interrupt::enable() };
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unsafe { T::Interrupt::enable() };
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Self { _p: spim }
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spim
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}
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}
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fn prepare(&mut self, rx: *mut [u8], tx: *const [u8]) -> Result<(), Error> {
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fn prepare(&mut self, rx: *mut [u8], tx: *const [u8]) -> Result<(), Error> {
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@ -169,47 +169,10 @@ impl<'d, T: Instance> Spis<'d, T> {
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// Enable SPIS instance.
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// Enable SPIS instance.
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r.enable.write(|w| w.enable().enabled());
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r.enable.write(|w| w.enable().enabled());
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// Configure mode.
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let mut spis = Self { _p: spis };
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let mode = config.mode;
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r.config.write(|w| {
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match mode {
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MODE_0 => {
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w.order().msb_first();
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w.cpol().active_high();
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w.cpha().leading();
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}
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MODE_1 => {
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w.order().msb_first();
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w.cpol().active_high();
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w.cpha().trailing();
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}
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MODE_2 => {
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w.order().msb_first();
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w.cpol().active_low();
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w.cpha().leading();
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}
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MODE_3 => {
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w.order().msb_first();
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w.cpol().active_low();
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w.cpha().trailing();
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}
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}
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w
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// Apply runtime peripheral configuration
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});
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Self::set_config(&mut spis, &config);
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// Set over-read character.
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let orc = config.orc;
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r.orc.write(|w| unsafe { w.orc().bits(orc) });
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// Set default character.
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let def = config.def;
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r.def.write(|w| unsafe { w.def().bits(def) });
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// Configure auto-acquire on 'transfer end' event.
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if config.auto_acquire {
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r.shorts.write(|w| w.end_acquire().bit(true));
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}
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// Disable all events interrupts.
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// Disable all events interrupts.
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r.intenclr.write(|w| unsafe { w.bits(0xFFFF_FFFF) });
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r.intenclr.write(|w| unsafe { w.bits(0xFFFF_FFFF) });
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@ -217,7 +180,7 @@ impl<'d, T: Instance> Spis<'d, T> {
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T::Interrupt::unpend();
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T::Interrupt::unpend();
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unsafe { T::Interrupt::enable() };
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unsafe { T::Interrupt::enable() };
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Self { _p: spis }
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spis
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}
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}
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fn prepare(&mut self, rx: *mut [u8], tx: *const [u8]) -> Result<(), Error> {
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fn prepare(&mut self, rx: *mut [u8], tx: *const [u8]) -> Result<(), Error> {
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@ -57,7 +57,6 @@ impl<'d> Temp<'d> {
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/// ```no_run
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/// ```no_run
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/// use embassy_nrf::{bind_interrupts, temp};
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/// use embassy_nrf::{bind_interrupts, temp};
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/// use embassy_nrf::temp::Temp;
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/// use embassy_nrf::temp::Temp;
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/// use embassy_time::{Duration, Timer};
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///
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///
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/// bind_interrupts!(struct Irqs {
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/// bind_interrupts!(struct Irqs {
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/// TEMP => temp::InterruptHandler;
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/// TEMP => temp::InterruptHandler;
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@ -167,9 +167,10 @@ impl<'d, T: Instance> Twim<'d, T> {
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// Enable TWIM instance.
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// Enable TWIM instance.
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r.enable.write(|w| w.enable().enabled());
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r.enable.write(|w| w.enable().enabled());
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// Configure frequency.
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let mut twim = Self { _p: twim };
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r.frequency
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.write(|w| unsafe { w.frequency().bits(config.frequency as u32) });
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// Apply runtime peripheral configuration
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Self::set_config(&mut twim, &config);
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// Disable all events interrupts
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// Disable all events interrupts
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r.intenclr.write(|w| unsafe { w.bits(0xFFFF_FFFF) });
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r.intenclr.write(|w| unsafe { w.bits(0xFFFF_FFFF) });
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@ -177,7 +178,7 @@ impl<'d, T: Instance> Twim<'d, T> {
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T::Interrupt::unpend();
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T::Interrupt::unpend();
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unsafe { T::Interrupt::enable() };
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unsafe { T::Interrupt::enable() };
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Self { _p: twim }
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twim
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}
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}
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/// Set TX buffer, checking that it is in RAM and has suitable length.
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/// Set TX buffer, checking that it is in RAM and has suitable length.
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