Merge pull request #1975 from tyler-gilbert/issue-1974-add-sai-driver
Issue 1974 add sai driver
This commit is contained in:
xoviat
GitHub
commit
7bc57ca3f7
4 changed files with 962 additions and 5 deletions
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@ -463,6 +463,15 @@ fn main() {
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(("lpuart", "RTS"), quote!(crate::usart::RtsPin)),
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(("lpuart", "CK"), quote!(crate::usart::CkPin)),
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(("lpuart", "DE"), quote!(crate::usart::DePin)),
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(("sai", "SCK_A"), quote!(crate::sai::SckAPin)),
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(("sai", "SCK_B"), quote!(crate::sai::SckBPin)),
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(("sai", "FS_A"), quote!(crate::sai::FsAPin)),
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(("sai", "FS_B"), quote!(crate::sai::FsBPin)),
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(("sai", "SD_A"), quote!(crate::sai::SdAPin)),
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(("sai", "SD_B"), quote!(crate::sai::SdBPin)),
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(("sai", "MCLK_A"), quote!(crate::sai::MclkAPin)),
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(("sai", "MCLK_B"), quote!(crate::sai::MclkBPin)),
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(("sai", "WS"), quote!(crate::sai::WsPin)),
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(("spi", "SCK"), quote!(crate::spi::SckPin)),
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(("spi", "MOSI"), quote!(crate::spi::MosiPin)),
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(("spi", "MISO"), quote!(crate::spi::MisoPin)),
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@ -750,6 +759,8 @@ fn main() {
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(("usart", "TX"), quote!(crate::usart::TxDma)),
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(("lpuart", "RX"), quote!(crate::usart::RxDma)),
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(("lpuart", "TX"), quote!(crate::usart::TxDma)),
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(("sai", "A"), quote!(crate::sai::DmaA)),
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(("sai", "B"), quote!(crate::sai::DmaB)),
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(("spi", "RX"), quote!(crate::spi::RxDma)),
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(("spi", "TX"), quote!(crate::spi::TxDma)),
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(("i2c", "RX"), quote!(crate::i2c::RxDma)),
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@ -55,6 +55,8 @@ pub mod qspi;
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pub mod rng;
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#[cfg(all(rtc, not(rtc_v1)))]
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pub mod rtc;
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#[cfg(sai)]
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pub mod sai;
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#[cfg(sdmmc)]
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pub mod sdmmc;
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#[cfg(spi)]
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@ -32,6 +32,9 @@ pub struct Config {
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#[cfg(not(any(stm32f410, stm32f411, stm32f412, stm32f413, stm32f423, stm32f446)))]
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pub plli2s: Option<Hertz>,
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#[cfg(any(stm32f427, stm32f429, stm32f437, stm32f439, stm32f446, stm32f469, stm32f479))]
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pub pllsai: Option<Hertz>,
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pub pll48: bool,
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pub rtc: Option<RtcClockSource>,
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pub lsi: bool,
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@ -50,10 +53,9 @@ fn setup_i2s_pll(_vco_in: u32, _plli2s: Option<u32>) -> Option<u32> {
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}
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#[cfg(not(any(stm32f410, stm32f411, stm32f412, stm32f413, stm32f423, stm32f446)))]
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fn setup_i2s_pll(vco_in: u32, plli2s: Option<u32>) -> Option<u32> {
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fn calculate_sai_i2s_pll_values(vco_in: u32, max_div: u32, target: Option<u32>) -> Option<(u32, u32, u32)> {
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let min_div = 2;
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let max_div = 7;
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let target = match plli2s {
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let target = match target {
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Some(target) => target,
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None => return None,
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};
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@ -77,15 +79,48 @@ fn setup_i2s_pll(vco_in: u32, plli2s: Option<u32>) -> Option<u32> {
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})
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.min_by_key(|(_, _, _, error)| *error)?;
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Some((n, outdiv, output))
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}
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#[cfg(not(any(stm32f410, stm32f411, stm32f412, stm32f413, stm32f423, stm32f446)))]
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fn setup_i2s_pll(vco_in: u32, plli2s: Option<u32>) -> Option<u32> {
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let (n, outdiv, output) = calculate_sai_i2s_pll_values(vco_in, 7, plli2s)?;
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RCC.plli2scfgr().modify(|w| {
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w.set_plli2sn(n as u16);
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w.set_plli2sr(outdiv as u8);
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#[cfg(any(stm32f427, stm32f429, stm32f437, stm32f439, stm32f446, stm32f469, stm32f479))]
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w.set_plli2sq(outdiv as u8); //set sai divider same as i2s
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});
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Some(output)
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}
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fn setup_pll(pllsrcclk: u32, use_hse: bool, pllsysclk: Option<u32>, plli2s: Option<u32>, pll48clk: bool) -> PllResults {
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#[cfg(not(any(stm32f427, stm32f429, stm32f437, stm32f439, stm32f446, stm32f469, stm32f479)))]
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fn setup_sai_pll(_vco_in: u32, _pllsai: Option<u32>) -> Option<u32> {
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None
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}
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#[cfg(any(stm32f427, stm32f429, stm32f437, stm32f439, stm32f446, stm32f469, stm32f479))]
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fn setup_sai_pll(vco_in: u32, pllsai: Option<u32>) -> Option<u32> {
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let (n, outdiv, output) = calculate_sai_i2s_pll_values(vco_in, 15, pllsai)?;
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RCC.pllsaicfgr().modify(|w| {
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w.set_pllsain(n as u16);
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w.set_pllsaiq(outdiv as u8);
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});
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Some(output)
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}
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fn setup_pll(
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pllsrcclk: u32,
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use_hse: bool,
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pllsysclk: Option<u32>,
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plli2s: Option<u32>,
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pllsai: Option<u32>,
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pll48clk: bool,
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) -> PllResults {
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use crate::pac::rcc::vals::{Pllp, Pllsrc};
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let sysclk = pllsysclk.unwrap_or(pllsrcclk);
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@ -97,6 +132,7 @@ fn setup_pll(pllsrcclk: u32, use_hse: bool, pllsysclk: Option<u32>, plli2s: Opti
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pllsysclk: None,
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pll48clk: None,
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plli2sclk: None,
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pllsaiclk: None,
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};
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}
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// Input divisor from PLL source clock, must result to frequency in
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@ -147,6 +183,7 @@ fn setup_pll(pllsrcclk: u32, use_hse: bool, pllsysclk: Option<u32>, plli2s: Opti
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w.set_pllp(Pllp::from_bits(pllp as u8));
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w.set_pllq(pllq as u8);
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w.set_pllsrc(Pllsrc::from_bits(use_hse as u8));
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w.set_pllr(0);
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});
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let real_pllsysclk = vco_in * plln / sysclk_div;
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@ -156,6 +193,7 @@ fn setup_pll(pllsrcclk: u32, use_hse: bool, pllsysclk: Option<u32>, plli2s: Opti
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pllsysclk: Some(real_pllsysclk),
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pll48clk: if pll48clk { Some(real_pll48clk) } else { None },
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plli2sclk: setup_i2s_pll(vco_in, plli2s),
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pllsaiclk: setup_sai_pll(vco_in, pllsai),
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}
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}
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@ -343,6 +381,10 @@ pub(crate) unsafe fn init(config: Config) {
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config.plli2s.map(|i2s| i2s.0),
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#[cfg(any(stm32f410, stm32f411, stm32f412, stm32f413, stm32f423, stm32f446))]
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None,
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#[cfg(any(stm32f427, stm32f429, stm32f437, stm32f439, stm32f446, stm32f469, stm32f479))]
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config.pllsai.map(|sai| sai.0),
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#[cfg(not(any(stm32f427, stm32f429, stm32f437, stm32f439, stm32f446, stm32f469, stm32f479)))]
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None,
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config.pll48,
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);
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@ -440,6 +482,12 @@ pub(crate) unsafe fn init(config: Config) {
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while !RCC.cr().read().plli2srdy() {}
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}
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#[cfg(any(stm32f427, stm32f429, stm32f437, stm32f439, stm32f446, stm32f469, stm32f479))]
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if plls.pllsaiclk.is_some() {
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RCC.cr().modify(|w| w.set_pllsaion(true));
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while !RCC.cr().read().pllsairdy() {}
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}
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RCC.cfgr().modify(|w| {
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w.set_ppre2(Ppre::from_bits(ppre2_bits));
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w.set_ppre1(Ppre::from_bits(ppre1_bits));
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@ -490,7 +538,7 @@ pub(crate) unsafe fn init(config: Config) {
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plli2s: plls.plli2sclk.map(Hertz),
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#[cfg(any(stm32f427, stm32f429, stm32f437, stm32f439, stm32f446, stm32f469, stm32f479))]
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pllsai: None,
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pllsai: plls.pllsaiclk.map(Hertz),
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rtc: rtc,
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rtc_hse: None,
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@ -503,6 +551,8 @@ struct PllResults {
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pll48clk: Option<u32>,
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#[allow(dead_code)]
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plli2sclk: Option<u32>,
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#[allow(dead_code)]
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pllsaiclk: Option<u32>,
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}
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mod max {
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894
embassy-stm32/src/sai/mod.rs
Normal file
894
embassy-stm32/src/sai/mod.rs
Normal file
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@ -0,0 +1,894 @@
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#![macro_use]
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use embassy_embedded_hal::SetConfig;
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use embassy_hal_internal::{into_ref, PeripheralRef};
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pub use crate::dma::word;
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use crate::dma::{ringbuffer, Channel, ReadableRingBuffer, TransferOptions, WritableRingBuffer};
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use crate::gpio::sealed::{AFType, Pin as _};
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use crate::gpio::AnyPin;
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use crate::pac::sai::{vals, Sai as Regs};
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use crate::rcc::RccPeripheral;
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use crate::{peripherals, Peripheral};
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#[derive(Debug)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub enum Error {
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NotATransmitter,
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NotAReceiver,
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OverrunError,
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}
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impl From<ringbuffer::OverrunError> for Error {
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fn from(_: ringbuffer::OverrunError) -> Self {
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Self::OverrunError
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}
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}
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#[derive(Copy, Clone)]
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pub enum SyncBlock {
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None,
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Sai1BlockA,
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Sai1BlockB,
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Sai2BlockA,
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Sai2BlockB,
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}
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#[derive(Copy, Clone)]
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pub enum SyncIn {
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None,
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ChannelZero,
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ChannelOne,
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}
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#[derive(Copy, Clone)]
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pub enum Mode {
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Master,
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Slave,
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}
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#[derive(Copy, Clone)]
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enum TxRx {
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Transmiter,
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Receiver,
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}
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impl Mode {
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#[cfg(any(sai_v1, sai_v2, sai_v3, sai_v4))]
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const fn mode(&self, tx_rx: TxRx) -> vals::Mode {
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match tx_rx {
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TxRx::Transmiter => match self {
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Mode::Master => vals::Mode::MASTERTX,
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Mode::Slave => vals::Mode::SLAVETX,
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},
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TxRx::Receiver => match self {
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Mode::Master => vals::Mode::MASTERRX,
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Mode::Slave => vals::Mode::SLAVERX,
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},
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}
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}
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}
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#[derive(Copy, Clone)]
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pub enum SlotSize {
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DataSize,
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/// 16 bit data length on 16 bit wide channel
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Channel16,
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/// 16 bit data length on 32 bit wide channel
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Channel32,
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}
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impl SlotSize {
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#[cfg(any(sai_v1, sai_v2, sai_v3, sai_v4))]
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pub const fn slotsz(&self) -> vals::Slotsz {
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match self {
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SlotSize::DataSize => vals::Slotsz::DATASIZE,
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SlotSize::Channel16 => vals::Slotsz::BIT16,
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SlotSize::Channel32 => vals::Slotsz::BIT32,
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}
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}
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}
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#[derive(Copy, Clone)]
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pub enum DataSize {
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Data8,
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Data10,
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Data16,
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Data20,
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Data24,
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Data32,
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}
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impl DataSize {
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#[cfg(any(sai_v1, sai_v2, sai_v3, sai_v4))]
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pub const fn ds(&self) -> vals::Ds {
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match self {
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DataSize::Data8 => vals::Ds::BIT8,
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DataSize::Data10 => vals::Ds::BIT10,
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DataSize::Data16 => vals::Ds::BIT16,
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DataSize::Data20 => vals::Ds::BIT20,
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DataSize::Data24 => vals::Ds::BIT24,
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DataSize::Data32 => vals::Ds::BIT32,
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}
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}
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}
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#[derive(Copy, Clone)]
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pub enum FifoThreshold {
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Empty,
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Quarter,
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Half,
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ThreeQuarters,
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Full,
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}
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impl FifoThreshold {
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#[cfg(any(sai_v1, sai_v2, sai_v3, sai_v4))]
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pub const fn fth(&self) -> vals::Fth {
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match self {
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FifoThreshold::Empty => vals::Fth::EMPTY,
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FifoThreshold::Quarter => vals::Fth::QUARTER1,
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FifoThreshold::Half => vals::Fth::QUARTER2,
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FifoThreshold::ThreeQuarters => vals::Fth::QUARTER3,
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FifoThreshold::Full => vals::Fth::FULL,
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}
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}
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}
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#[derive(Copy, Clone)]
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pub enum FifoLevel {
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Empty,
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FirstQuarter,
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SecondQuarter,
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ThirdQuarter,
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FourthQuarter,
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Full,
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}
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#[cfg(any(sai_v1, sai_v2, sai_v3, sai_v4))]
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impl From<vals::Flvl> for FifoLevel {
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fn from(flvl: vals::Flvl) -> Self {
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match flvl {
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vals::Flvl::EMPTY => FifoLevel::Empty,
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vals::Flvl::QUARTER1 => FifoLevel::FirstQuarter,
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vals::Flvl::QUARTER2 => FifoLevel::SecondQuarter,
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vals::Flvl::QUARTER3 => FifoLevel::ThirdQuarter,
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vals::Flvl::QUARTER4 => FifoLevel::FourthQuarter,
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vals::Flvl::FULL => FifoLevel::Full,
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_ => FifoLevel::Empty,
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}
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}
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}
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#[derive(Copy, Clone)]
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pub enum MuteDetection {
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NoMute,
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Mute,
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}
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#[derive(Copy, Clone)]
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pub enum MuteValue {
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Zero,
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LastValue,
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}
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impl MuteValue {
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#[cfg(any(sai_v1, sai_v2, sai_v3, sai_v4))]
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pub const fn muteval(&self) -> vals::Muteval {
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match self {
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MuteValue::Zero => vals::Muteval::SENDZERO,
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MuteValue::LastValue => vals::Muteval::SENDLAST,
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}
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}
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}
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#[derive(Copy, Clone)]
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pub enum OverUnderStatus {
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NoError,
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OverUnderRunDetected,
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}
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#[derive(Copy, Clone)]
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pub enum Protocol {
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Free,
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Spdif,
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Ac97,
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}
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impl Protocol {
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#[cfg(any(sai_v1, sai_v2, sai_v3, sai_v4))]
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pub const fn prtcfg(&self) -> vals::Prtcfg {
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match self {
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Protocol::Free => vals::Prtcfg::FREE,
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Protocol::Spdif => vals::Prtcfg::SPDIF,
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Protocol::Ac97 => vals::Prtcfg::AC97,
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}
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}
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}
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#[derive(Copy, Clone)]
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pub enum SyncEnable {
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Asynchronous,
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/// Syncs with the other A/B sub-block within the SAI unit
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Internal,
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/// Syncs with a sub-block in the other SAI unit - use set_sync_output() and set_sync_input()
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External,
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}
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impl SyncEnable {
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#[cfg(any(sai_v1, sai_v2, sai_v3, sai_v4))]
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pub const fn syncen(&self) -> vals::Syncen {
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match self {
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SyncEnable::Asynchronous => vals::Syncen::ASYNCHRONOUS,
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SyncEnable::Internal => vals::Syncen::INTERNAL,
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SyncEnable::External => vals::Syncen::EXTERNAL,
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}
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}
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}
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#[derive(Copy, Clone, PartialEq)]
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pub enum StereoMono {
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Stereo,
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Mono,
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}
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impl StereoMono {
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#[cfg(any(sai_v1, sai_v2, sai_v3, sai_v4))]
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pub const fn mono(&self) -> vals::Mono {
|
||||
match self {
|
||||
StereoMono::Stereo => vals::Mono::STEREO,
|
||||
StereoMono::Mono => vals::Mono::MONO,
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
#[derive(Copy, Clone)]
|
||||
pub enum BitOrder {
|
||||
LsbFirst,
|
||||
MsbFirst,
|
||||
}
|
||||
|
||||
impl BitOrder {
|
||||
#[cfg(any(sai_v1, sai_v2, sai_v3, sai_v4))]
|
||||
pub const fn lsbfirst(&self) -> vals::Lsbfirst {
|
||||
match self {
|
||||
BitOrder::LsbFirst => vals::Lsbfirst::LSBFIRST,
|
||||
BitOrder::MsbFirst => vals::Lsbfirst::MSBFIRST,
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
#[derive(Copy, Clone)]
|
||||
pub enum FrameSyncOffset {
|
||||
/// This is used in modes other than standard I2S phillips mode
|
||||
OnFirstBit,
|
||||
/// This is used in standard I2S phillips mode
|
||||
BeforeFirstBit,
|
||||
}
|
||||
|
||||
impl FrameSyncOffset {
|
||||
#[cfg(any(sai_v1, sai_v2, sai_v3, sai_v4))]
|
||||
pub const fn fsoff(&self) -> vals::Fsoff {
|
||||
match self {
|
||||
FrameSyncOffset::OnFirstBit => vals::Fsoff::ONFIRST,
|
||||
FrameSyncOffset::BeforeFirstBit => vals::Fsoff::BEFOREFIRST,
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
#[derive(Copy, Clone)]
|
||||
pub enum FrameSyncPolarity {
|
||||
ActiveLow,
|
||||
ActiveHigh,
|
||||
}
|
||||
|
||||
impl FrameSyncPolarity {
|
||||
#[cfg(any(sai_v1, sai_v2, sai_v3, sai_v4))]
|
||||
pub const fn fspol(&self) -> vals::Fspol {
|
||||
match self {
|
||||
FrameSyncPolarity::ActiveLow => vals::Fspol::FALLINGEDGE,
|
||||
FrameSyncPolarity::ActiveHigh => vals::Fspol::RISINGEDGE,
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
#[derive(Copy, Clone)]
|
||||
pub enum FrameSyncDefinition {
|
||||
StartOfFrame,
|
||||
ChannelIdentification,
|
||||
}
|
||||
|
||||
impl FrameSyncDefinition {
|
||||
#[cfg(any(sai_v1, sai_v2, sai_v3, sai_v4))]
|
||||
pub const fn fsdef(&self) -> bool {
|
||||
match self {
|
||||
FrameSyncDefinition::StartOfFrame => false,
|
||||
FrameSyncDefinition::ChannelIdentification => true,
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
#[derive(Copy, Clone)]
|
||||
pub enum ClockStrobe {
|
||||
Falling,
|
||||
Rising,
|
||||
}
|
||||
|
||||
impl ClockStrobe {
|
||||
#[cfg(any(sai_v1, sai_v2, sai_v3, sai_v4))]
|
||||
pub const fn ckstr(&self) -> vals::Ckstr {
|
||||
match self {
|
||||
ClockStrobe::Falling => vals::Ckstr::FALLINGEDGE,
|
||||
ClockStrobe::Rising => vals::Ckstr::RISINGEDGE,
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
#[derive(Copy, Clone)]
|
||||
pub enum ComplementFormat {
|
||||
OnesComplement,
|
||||
TwosComplement,
|
||||
}
|
||||
|
||||
impl ComplementFormat {
|
||||
#[cfg(any(sai_v1, sai_v2, sai_v3, sai_v4))]
|
||||
pub const fn cpl(&self) -> vals::Cpl {
|
||||
match self {
|
||||
ComplementFormat::OnesComplement => vals::Cpl::ONESCOMPLEMENT,
|
||||
ComplementFormat::TwosComplement => vals::Cpl::TWOSCOMPLEMENT,
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
#[derive(Copy, Clone)]
|
||||
pub enum Companding {
|
||||
None,
|
||||
MuLaw,
|
||||
ALaw,
|
||||
}
|
||||
|
||||
impl Companding {
|
||||
#[cfg(any(sai_v1, sai_v2, sai_v3, sai_v4))]
|
||||
pub const fn comp(&self) -> vals::Comp {
|
||||
match self {
|
||||
Companding::None => vals::Comp::NOCOMPANDING,
|
||||
Companding::MuLaw => vals::Comp::MULAW,
|
||||
Companding::ALaw => vals::Comp::ALAW,
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
#[derive(Copy, Clone)]
|
||||
pub enum OutputDrive {
|
||||
OnStart,
|
||||
Immediately,
|
||||
}
|
||||
|
||||
impl OutputDrive {
|
||||
#[cfg(any(sai_v1, sai_v2, sai_v3, sai_v4))]
|
||||
pub const fn outdriv(&self) -> vals::Outdriv {
|
||||
match self {
|
||||
OutputDrive::OnStart => vals::Outdriv::ONSTART,
|
||||
OutputDrive::Immediately => vals::Outdriv::IMMEDIATELY,
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
#[derive(Copy, Clone, PartialEq)]
|
||||
pub enum MasterClockDivider {
|
||||
MasterClockDisabled,
|
||||
Div1,
|
||||
Div2,
|
||||
Div4,
|
||||
Div6,
|
||||
Div8,
|
||||
Div10,
|
||||
Div12,
|
||||
Div14,
|
||||
Div16,
|
||||
Div18,
|
||||
Div20,
|
||||
Div22,
|
||||
Div24,
|
||||
Div26,
|
||||
Div28,
|
||||
Div30,
|
||||
}
|
||||
|
||||
impl MasterClockDivider {
|
||||
#[cfg(any(sai_v1, sai_v2, sai_v3, sai_v4))]
|
||||
pub const fn mckdiv(&self) -> u8 {
|
||||
match self {
|
||||
MasterClockDivider::MasterClockDisabled => 0,
|
||||
MasterClockDivider::Div1 => 0,
|
||||
MasterClockDivider::Div2 => 1,
|
||||
MasterClockDivider::Div4 => 2,
|
||||
MasterClockDivider::Div6 => 3,
|
||||
MasterClockDivider::Div8 => 4,
|
||||
MasterClockDivider::Div10 => 5,
|
||||
MasterClockDivider::Div12 => 6,
|
||||
MasterClockDivider::Div14 => 7,
|
||||
MasterClockDivider::Div16 => 8,
|
||||
MasterClockDivider::Div18 => 9,
|
||||
MasterClockDivider::Div20 => 10,
|
||||
MasterClockDivider::Div22 => 11,
|
||||
MasterClockDivider::Div24 => 12,
|
||||
MasterClockDivider::Div26 => 13,
|
||||
MasterClockDivider::Div28 => 14,
|
||||
MasterClockDivider::Div30 => 15,
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/// [`SAI`] configuration.
|
||||
#[non_exhaustive]
|
||||
#[derive(Copy, Clone)]
|
||||
pub struct Config {
|
||||
pub mode: Mode,
|
||||
pub sync_enable: SyncEnable,
|
||||
pub is_sync_output: bool,
|
||||
pub protocol: Protocol,
|
||||
pub slot_size: SlotSize,
|
||||
pub slot_count: word::U4,
|
||||
pub slot_enable: u16,
|
||||
pub first_bit_offset: word::U5,
|
||||
pub data_size: DataSize,
|
||||
pub stereo_mono: StereoMono,
|
||||
pub bit_order: BitOrder,
|
||||
pub frame_sync_offset: FrameSyncOffset,
|
||||
pub frame_sync_polarity: FrameSyncPolarity,
|
||||
pub frame_sync_active_level_length: word::U7,
|
||||
pub frame_sync_definition: FrameSyncDefinition,
|
||||
pub frame_length: u8,
|
||||
pub clock_strobe: ClockStrobe,
|
||||
pub output_drive: OutputDrive,
|
||||
pub master_clock_divider: MasterClockDivider,
|
||||
pub is_high_impedenane_on_inactive_slot: bool,
|
||||
pub fifo_threshold: FifoThreshold,
|
||||
pub companding: Companding,
|
||||
pub complement_format: ComplementFormat,
|
||||
pub mute_value: MuteValue,
|
||||
pub mute_detection_counter: word::U5,
|
||||
}
|
||||
|
||||
impl Default for Config {
|
||||
fn default() -> Self {
|
||||
Self {
|
||||
mode: Mode::Master,
|
||||
is_sync_output: false,
|
||||
sync_enable: SyncEnable::Asynchronous,
|
||||
protocol: Protocol::Free,
|
||||
slot_size: SlotSize::DataSize,
|
||||
slot_count: word::U4(2),
|
||||
first_bit_offset: word::U5(0),
|
||||
slot_enable: 0b11,
|
||||
data_size: DataSize::Data16,
|
||||
stereo_mono: StereoMono::Stereo,
|
||||
bit_order: BitOrder::LsbFirst,
|
||||
frame_sync_offset: FrameSyncOffset::BeforeFirstBit,
|
||||
frame_sync_polarity: FrameSyncPolarity::ActiveLow,
|
||||
frame_sync_active_level_length: word::U7(16),
|
||||
frame_sync_definition: FrameSyncDefinition::ChannelIdentification,
|
||||
frame_length: 32,
|
||||
master_clock_divider: MasterClockDivider::MasterClockDisabled,
|
||||
clock_strobe: ClockStrobe::Rising,
|
||||
output_drive: OutputDrive::Immediately,
|
||||
is_high_impedenane_on_inactive_slot: false,
|
||||
fifo_threshold: FifoThreshold::ThreeQuarters,
|
||||
companding: Companding::None,
|
||||
complement_format: ComplementFormat::TwosComplement,
|
||||
mute_value: MuteValue::Zero,
|
||||
mute_detection_counter: word::U5(4),
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
impl Config {
|
||||
pub fn new_i2s() -> Self {
|
||||
return Default::default();
|
||||
}
|
||||
|
||||
pub fn new_msb_first() -> Self {
|
||||
Self {
|
||||
bit_order: BitOrder::MsbFirst,
|
||||
frame_sync_offset: FrameSyncOffset::OnFirstBit,
|
||||
..Default::default()
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
#[derive(Copy, Clone)]
|
||||
pub enum SubBlock {
|
||||
A = 0,
|
||||
B = 1,
|
||||
}
|
||||
|
||||
enum RingBuffer<'d, C: Channel, W: word::Word> {
|
||||
Writable(WritableRingBuffer<'d, C, W>),
|
||||
#[allow(dead_code)] // remove this after implementing new_* functions for receiver
|
||||
Readable(ReadableRingBuffer<'d, C, W>),
|
||||
}
|
||||
|
||||
#[cfg(any(sai_v1, sai_v2, sai_v3, sai_v4))]
|
||||
fn wdr<W: word::Word>(w: crate::pac::sai::Sai, sub_block: SubBlock) -> *mut W {
|
||||
let ch = w.ch(sub_block as usize);
|
||||
ch.dr().as_ptr() as _
|
||||
}
|
||||
|
||||
pub struct Sai<'d, T: Instance, C: Channel, W: word::Word> {
|
||||
_peri: PeripheralRef<'d, T>,
|
||||
sd: Option<PeripheralRef<'d, AnyPin>>,
|
||||
fs: Option<PeripheralRef<'d, AnyPin>>,
|
||||
sck: Option<PeripheralRef<'d, AnyPin>>,
|
||||
mclk: Option<PeripheralRef<'d, AnyPin>>,
|
||||
ring_buffer: RingBuffer<'d, C, W>,
|
||||
sub_block: SubBlock,
|
||||
}
|
||||
|
||||
impl<'d, T: Instance, C: Channel, W: word::Word> Sai<'d, T, C, W> {
|
||||
fn get_transmitter_af_types(mode: Mode) -> (AFType, AFType) {
|
||||
match mode {
|
||||
Mode::Master => (AFType::OutputPushPull, AFType::OutputPushPull),
|
||||
Mode::Slave => (AFType::OutputPushPull, AFType::Input),
|
||||
}
|
||||
}
|
||||
|
||||
pub fn new_asynchronous_transmitter_with_mclk_a(
|
||||
peri: impl Peripheral<P = T> + 'd,
|
||||
sck: impl Peripheral<P = impl SckAPin<T>> + 'd,
|
||||
sd: impl Peripheral<P = impl SdAPin<T>> + 'd,
|
||||
fs: impl Peripheral<P = impl FsAPin<T>> + 'd,
|
||||
mclk: impl Peripheral<P = impl MclkAPin<T>> + 'd,
|
||||
dma: impl Peripheral<P = C> + 'd,
|
||||
dma_buf: &'d mut [W],
|
||||
mut config: Config,
|
||||
) -> Self
|
||||
where
|
||||
C: Channel + DmaA<T>,
|
||||
{
|
||||
into_ref!(mclk);
|
||||
|
||||
mclk.set_as_af(mclk.af_num(), AFType::OutputPushPull);
|
||||
mclk.set_speed(crate::gpio::Speed::VeryHigh);
|
||||
|
||||
if config.master_clock_divider == MasterClockDivider::MasterClockDisabled {
|
||||
config.master_clock_divider = MasterClockDivider::Div1;
|
||||
}
|
||||
|
||||
Self::new_asynchronous_transmitter_a(peri, sck, sd, fs, dma, dma_buf, config)
|
||||
}
|
||||
|
||||
pub fn new_asynchronous_transmitter_a(
|
||||
peri: impl Peripheral<P = T> + 'd,
|
||||
sck: impl Peripheral<P = impl SckAPin<T>> + 'd,
|
||||
sd: impl Peripheral<P = impl SdAPin<T>> + 'd,
|
||||
fs: impl Peripheral<P = impl FsAPin<T>> + 'd,
|
||||
dma: impl Peripheral<P = C> + 'd,
|
||||
dma_buf: &'d mut [W],
|
||||
config: Config,
|
||||
) -> Self
|
||||
where
|
||||
C: Channel + DmaA<T>,
|
||||
{
|
||||
into_ref!(peri, dma, sck, sd, fs);
|
||||
|
||||
let (sd_af_type, ck_af_type) = Self::get_transmitter_af_types(config.mode);
|
||||
sd.set_as_af(sd.af_num(), sd_af_type);
|
||||
sd.set_speed(crate::gpio::Speed::VeryHigh);
|
||||
|
||||
sck.set_as_af(sck.af_num(), ck_af_type);
|
||||
sck.set_speed(crate::gpio::Speed::VeryHigh);
|
||||
fs.set_as_af(fs.af_num(), ck_af_type);
|
||||
fs.set_speed(crate::gpio::Speed::VeryHigh);
|
||||
|
||||
let request = dma.request();
|
||||
let opts = TransferOptions {
|
||||
half_transfer_ir: true,
|
||||
circular: true,
|
||||
..Default::default()
|
||||
};
|
||||
|
||||
let sub_block = SubBlock::A;
|
||||
|
||||
Self::new_inner(
|
||||
peri,
|
||||
sub_block,
|
||||
Some(sck.map_into()),
|
||||
None,
|
||||
Some(sd.map_into()),
|
||||
Some(fs.map_into()),
|
||||
RingBuffer::Writable(unsafe {
|
||||
WritableRingBuffer::new_write(dma, request, wdr(T::REGS, sub_block), dma_buf, opts)
|
||||
}),
|
||||
config,
|
||||
)
|
||||
}
|
||||
|
||||
pub fn new_asynchronous_transmitter_with_mclk_b(
|
||||
peri: impl Peripheral<P = T> + 'd,
|
||||
sck: impl Peripheral<P = impl SckBPin<T>> + 'd,
|
||||
sd: impl Peripheral<P = impl SdBPin<T>> + 'd,
|
||||
fs: impl Peripheral<P = impl FsBPin<T>> + 'd,
|
||||
mclk: impl Peripheral<P = impl MclkBPin<T>> + 'd,
|
||||
dma: impl Peripheral<P = C> + 'd,
|
||||
dma_buf: &'d mut [W],
|
||||
mut config: Config,
|
||||
) -> Self
|
||||
where
|
||||
C: Channel + DmaB<T>,
|
||||
{
|
||||
into_ref!(mclk);
|
||||
|
||||
mclk.set_as_af(mclk.af_num(), AFType::OutputPushPull);
|
||||
mclk.set_speed(crate::gpio::Speed::VeryHigh);
|
||||
|
||||
if config.master_clock_divider == MasterClockDivider::MasterClockDisabled {
|
||||
config.master_clock_divider = MasterClockDivider::Div1;
|
||||
}
|
||||
|
||||
Self::new_asynchronous_transmitter_b(peri, sck, sd, fs, dma, dma_buf, config)
|
||||
}
|
||||
|
||||
pub fn new_asynchronous_transmitter_b(
|
||||
peri: impl Peripheral<P = T> + 'd,
|
||||
sck: impl Peripheral<P = impl SckBPin<T>> + 'd,
|
||||
sd: impl Peripheral<P = impl SdBPin<T>> + 'd,
|
||||
fs: impl Peripheral<P = impl FsBPin<T>> + 'd,
|
||||
dma: impl Peripheral<P = C> + 'd,
|
||||
dma_buf: &'d mut [W],
|
||||
config: Config,
|
||||
) -> Self
|
||||
where
|
||||
C: Channel + DmaB<T>,
|
||||
{
|
||||
into_ref!(dma, peri, sck, sd, fs);
|
||||
|
||||
let (sd_af_type, ck_af_type) = Self::get_transmitter_af_types(config.mode);
|
||||
|
||||
sd.set_as_af(sd.af_num(), sd_af_type);
|
||||
sd.set_speed(crate::gpio::Speed::VeryHigh);
|
||||
|
||||
sck.set_as_af(sck.af_num(), ck_af_type);
|
||||
sck.set_speed(crate::gpio::Speed::VeryHigh);
|
||||
fs.set_as_af(fs.af_num(), ck_af_type);
|
||||
fs.set_speed(crate::gpio::Speed::VeryHigh);
|
||||
|
||||
let request = dma.request();
|
||||
let opts = TransferOptions {
|
||||
half_transfer_ir: true,
|
||||
..Default::default()
|
||||
};
|
||||
|
||||
let sub_block = SubBlock::B;
|
||||
|
||||
Self::new_inner(
|
||||
peri,
|
||||
sub_block,
|
||||
Some(sck.map_into()),
|
||||
None,
|
||||
Some(sd.map_into()),
|
||||
Some(fs.map_into()),
|
||||
RingBuffer::Writable(unsafe {
|
||||
WritableRingBuffer::new_write(dma, request, wdr(T::REGS, sub_block), dma_buf, opts)
|
||||
}),
|
||||
config,
|
||||
)
|
||||
}
|
||||
|
||||
pub fn start(self: &mut Self) {
|
||||
match self.ring_buffer {
|
||||
RingBuffer::Writable(ref mut rb) => {
|
||||
rb.start();
|
||||
}
|
||||
RingBuffer::Readable(ref mut rb) => {
|
||||
rb.start();
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
fn is_transmitter(ring_buffer: &RingBuffer<C, W>) -> bool {
|
||||
match ring_buffer {
|
||||
RingBuffer::Writable(_) => true,
|
||||
_ => false,
|
||||
}
|
||||
}
|
||||
|
||||
fn new_inner(
|
||||
peri: impl Peripheral<P = T> + 'd,
|
||||
sub_block: SubBlock,
|
||||
sck: Option<PeripheralRef<'d, AnyPin>>,
|
||||
mclk: Option<PeripheralRef<'d, AnyPin>>,
|
||||
sd: Option<PeripheralRef<'d, AnyPin>>,
|
||||
fs: Option<PeripheralRef<'d, AnyPin>>,
|
||||
ring_buffer: RingBuffer<'d, C, W>,
|
||||
config: Config,
|
||||
) -> Self {
|
||||
T::enable();
|
||||
T::reset();
|
||||
|
||||
#[cfg(any(sai_v4))]
|
||||
{
|
||||
// Not totally clear from the datasheet if this is right
|
||||
// This is only used if using SyncEnable::External
|
||||
let value: u8 = if T::REGS.as_ptr() == stm32_metapac::SAI1.as_ptr() {
|
||||
1 //this is SAI1, so sync with SAI2
|
||||
} else {
|
||||
0 //this is SAI2, so sync with SAI1
|
||||
};
|
||||
T::REGS.gcr().modify(|w| {
|
||||
w.set_syncin(value);
|
||||
});
|
||||
|
||||
if config.is_sync_output {
|
||||
let syncout: u8 = match sub_block {
|
||||
SubBlock::A => 0b01,
|
||||
SubBlock::B => 0b10,
|
||||
};
|
||||
T::REGS.gcr().modify(|w| {
|
||||
w.set_syncout(syncout);
|
||||
});
|
||||
}
|
||||
}
|
||||
|
||||
#[cfg(any(sai_v1, sai_v2, sai_v3, sai_v4))]
|
||||
{
|
||||
let ch = T::REGS.ch(sub_block as usize);
|
||||
ch.cr1().modify(|w| {
|
||||
w.set_mode(config.mode.mode(if Self::is_transmitter(&ring_buffer) {
|
||||
TxRx::Transmiter
|
||||
} else {
|
||||
TxRx::Receiver
|
||||
}));
|
||||
w.set_prtcfg(config.protocol.prtcfg());
|
||||
w.set_ds(config.data_size.ds());
|
||||
w.set_lsbfirst(config.bit_order.lsbfirst());
|
||||
w.set_ckstr(config.clock_strobe.ckstr());
|
||||
w.set_syncen(config.sync_enable.syncen());
|
||||
w.set_mono(config.stereo_mono.mono());
|
||||
w.set_outdriv(config.output_drive.outdriv());
|
||||
w.set_mckdiv(config.master_clock_divider.mckdiv());
|
||||
w.set_nodiv(
|
||||
if config.master_clock_divider == MasterClockDivider::MasterClockDisabled {
|
||||
vals::Nodiv::NODIV
|
||||
} else {
|
||||
vals::Nodiv::MASTERCLOCK
|
||||
},
|
||||
);
|
||||
w.set_dmaen(true);
|
||||
});
|
||||
|
||||
ch.cr2().modify(|w| {
|
||||
w.set_fth(config.fifo_threshold.fth());
|
||||
w.set_comp(config.companding.comp());
|
||||
w.set_cpl(config.complement_format.cpl());
|
||||
w.set_muteval(config.mute_value.muteval());
|
||||
w.set_mutecnt(config.mute_detection_counter.0 as u8);
|
||||
w.set_tris(config.is_high_impedenane_on_inactive_slot);
|
||||
});
|
||||
|
||||
ch.frcr().modify(|w| {
|
||||
w.set_fsoff(config.frame_sync_offset.fsoff());
|
||||
w.set_fspol(config.frame_sync_polarity.fspol());
|
||||
w.set_fsdef(config.frame_sync_definition.fsdef());
|
||||
w.set_fsall(config.frame_sync_active_level_length.0 as u8);
|
||||
w.set_frl(config.frame_length - 1);
|
||||
});
|
||||
|
||||
ch.slotr().modify(|w| {
|
||||
w.set_nbslot(config.slot_count.0 as u8 - 1);
|
||||
w.set_slotsz(config.slot_size.slotsz());
|
||||
w.set_fboff(config.first_bit_offset.0 as u8);
|
||||
w.set_sloten(vals::Sloten(config.slot_enable as u16));
|
||||
});
|
||||
|
||||
ch.cr1().modify(|w| w.set_saien(true));
|
||||
}
|
||||
|
||||
Self {
|
||||
_peri: peri.into_ref(),
|
||||
sub_block,
|
||||
sck,
|
||||
mclk,
|
||||
sd,
|
||||
fs,
|
||||
ring_buffer,
|
||||
}
|
||||
}
|
||||
|
||||
pub fn flush(&mut self) {
|
||||
let ch = T::REGS.ch(self.sub_block as usize);
|
||||
ch.cr1().modify(|w| w.set_saien(false));
|
||||
#[cfg(any(sai_v1, sai_v2))]
|
||||
{
|
||||
ch.cr2().modify(|w| w.set_fflush(vals::Fflush::FLUSH));
|
||||
}
|
||||
#[cfg(any(sai_v3, sai_v4))]
|
||||
{
|
||||
ch.cr2().modify(|w| w.set_fflush(true));
|
||||
}
|
||||
ch.cr1().modify(|w| w.set_saien(true));
|
||||
}
|
||||
|
||||
pub fn set_mute(&mut self, value: bool) {
|
||||
let ch = T::REGS.ch(self.sub_block as usize);
|
||||
ch.cr2().modify(|w| w.set_mute(value));
|
||||
}
|
||||
|
||||
/// Reconfigures it with the supplied config.
|
||||
pub fn reconfigure(&mut self, _config: Config) {}
|
||||
|
||||
pub fn get_current_config(&self) -> Config {
|
||||
Config::default()
|
||||
}
|
||||
|
||||
pub async fn write(&mut self, data: &[W]) -> Result<(), Error> {
|
||||
match &mut self.ring_buffer {
|
||||
RingBuffer::Writable(buffer) => {
|
||||
buffer.write_exact(data).await?;
|
||||
Ok(())
|
||||
}
|
||||
_ => return Err(Error::NotATransmitter),
|
||||
}
|
||||
}
|
||||
|
||||
pub async fn read(&mut self, data: &mut [W]) -> Result<(), Error> {
|
||||
match &mut self.ring_buffer {
|
||||
RingBuffer::Readable(buffer) => {
|
||||
buffer.read_exact(data).await?;
|
||||
Ok(())
|
||||
}
|
||||
_ => Err(Error::NotAReceiver),
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
impl<'d, T: Instance, C: Channel, W: word::Word> Drop for Sai<'d, T, C, W> {
|
||||
fn drop(&mut self) {
|
||||
let ch = T::REGS.ch(self.sub_block as usize);
|
||||
ch.cr1().modify(|w| w.set_saien(false));
|
||||
self.fs.as_ref().map(|x| x.set_as_disconnected());
|
||||
self.sd.as_ref().map(|x| x.set_as_disconnected());
|
||||
self.sck.as_ref().map(|x| x.set_as_disconnected());
|
||||
self.mclk.as_ref().map(|x| x.set_as_disconnected());
|
||||
}
|
||||
}
|
||||
|
||||
pub(crate) mod sealed {
|
||||
use super::*;
|
||||
|
||||
pub trait Instance {
|
||||
const REGS: Regs;
|
||||
}
|
||||
}
|
||||
|
||||
pub trait Word: word::Word {}
|
||||
|
||||
pub trait Instance: Peripheral<P = Self> + sealed::Instance + RccPeripheral {}
|
||||
pin_trait!(SckAPin, Instance);
|
||||
pin_trait!(SckBPin, Instance);
|
||||
pin_trait!(FsAPin, Instance);
|
||||
pin_trait!(FsBPin, Instance);
|
||||
pin_trait!(SdAPin, Instance);
|
||||
pin_trait!(SdBPin, Instance);
|
||||
pin_trait!(MclkAPin, Instance);
|
||||
pin_trait!(MclkBPin, Instance);
|
||||
|
||||
dma_trait!(DmaA, Instance);
|
||||
dma_trait!(DmaB, Instance);
|
||||
|
||||
foreach_peripheral!(
|
||||
(sai, $inst:ident) => {
|
||||
impl sealed::Instance for peripherals::$inst {
|
||||
const REGS: Regs = crate::pac::$inst;
|
||||
}
|
||||
|
||||
impl Instance for peripherals::$inst {}
|
||||
};
|
||||
);
|
||||
|
||||
impl<'d, T: Instance, C: Channel, W: word::Word> SetConfig for Sai<'d, T, C, W> {
|
||||
type Config = Config;
|
||||
fn set_config(&mut self, config: &Self::Config) {
|
||||
self.reconfigure(*config);
|
||||
}
|
||||
}
|
||||
Loading…
Reference in a new issue