stm32: Add G0 USB RCC
Add configuration for STM32G0 USB clock.
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591c404813
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1 changed files with 50 additions and 1 deletions
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@ -72,6 +72,22 @@ pub enum PllSource {
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HSE(Hertz, HseMode),
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HSE(Hertz, HseMode),
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}
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}
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/// Sets the source for the 48MHz clock to the USB peripheral.
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#[cfg(any(stm32g0b1, stm32g0c1, stm32g0b0))]
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pub enum UsbSrc {
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/// Use the High Speed Internal Oscillator. The CRS must be used to calibrate the
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/// oscillator to comply with the USB specification for oscillator tolerance.
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#[cfg(any(stm32g0b1, stm32g0c1))]
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Hsi48(super::Hsi48Config),
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/// Use the PLLQ output. The PLL must be configured to output a 48MHz clock. The
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/// PLL needs to be using the HSE source to comply with the USB specification for oscillator
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/// tolerance.
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PllQ,
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/// Use the HSE source directly. The HSE must be a 48MHz source. The HSE source must comply
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/// with the USB specification for oscillator tolerance.
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HSE,
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}
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/// Clocks configutation
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/// Clocks configutation
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pub struct Config {
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pub struct Config {
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pub mux: ClockSrc,
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pub mux: ClockSrc,
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@ -79,6 +95,8 @@ pub struct Config {
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pub apb_pre: APBPrescaler,
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pub apb_pre: APBPrescaler,
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pub low_power_run: bool,
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pub low_power_run: bool,
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pub ls: super::LsConfig,
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pub ls: super::LsConfig,
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#[cfg(any(stm32g0b1, stm32g0c1, stm32g0b0))]
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pub usb_src: Option<UsbSrc>,
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}
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}
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impl Default for Config {
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impl Default for Config {
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@ -90,6 +108,8 @@ impl Default for Config {
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apb_pre: APBPrescaler::DIV1,
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apb_pre: APBPrescaler::DIV1,
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low_power_run: false,
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low_power_run: false,
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ls: Default::default(),
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ls: Default::default(),
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#[cfg(any(stm32g0b1, stm32g0c1, stm32g0b0))]
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usb_src: None,
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}
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}
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}
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}
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}
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}
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@ -303,13 +323,42 @@ pub(crate) unsafe fn init(config: Config) {
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let lsi_freq = (sw == Sw::LSI).then_some(super::LSI_FREQ);
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let lsi_freq = (sw == Sw::LSI).then_some(super::LSI_FREQ);
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let hse_freq = (sw == Sw::HSE).then_some(sys_clk);
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let hse_freq = (sw == Sw::HSE).then_some(sys_clk);
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#[cfg(any(stm32g0b1, stm32g0c1, stm32g0b0))]
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let hsi48_freq = config.usb_src.and_then(|config| {
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match config {
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UsbSrc::PllQ => {
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// Make sure the PLLQ is enabled and running at 48Mhz
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assert!(pll1_q_freq.is_some() && pll1_q_freq.unwrap().0 == 48_000_000);
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RCC.ccipr2()
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.modify(|w| w.set_usbsel(crate::pac::rcc::vals::Usbsel::PLL1_Q));
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None
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}
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UsbSrc::HSE => {
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// Make sure the HSE is enabled and running at 48Mhz
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assert!(hse_freq.is_some() && hse_freq.unwrap().0 == 48_000_000);
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RCC.ccipr2()
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.modify(|w| w.set_usbsel(crate::pac::rcc::vals::Usbsel::HSE));
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None
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}
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#[cfg(any(stm32g0b1, stm32g0c1))]
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UsbSrc::Hsi48(config) => {
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let freq = super::init_hsi48(config);
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RCC.ccipr2()
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.modify(|w| w.set_usbsel(crate::pac::rcc::vals::Usbsel::HSI48));
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Some(freq)
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}
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}
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});
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#[cfg(not(any(stm32g0b1, stm32g0c1, stm32g0b0)))]
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let hsi48_freq: Option<Hertz> = None;
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set_freqs(Clocks {
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set_freqs(Clocks {
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sys: sys_clk,
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sys: sys_clk,
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hclk1: ahb_freq,
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hclk1: ahb_freq,
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pclk1: apb_freq,
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pclk1: apb_freq,
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pclk1_tim: apb_tim_freq,
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pclk1_tim: apb_tim_freq,
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hsi: hsi_freq,
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hsi: hsi_freq,
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hsi48: None,
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hsi48: hsi48_freq,
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hsi_div_8: hsi_div_8_freq,
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hsi_div_8: hsi_div_8_freq,
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hse: hse_freq,
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hse: hse_freq,
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lse: lse_freq,
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lse: lse_freq,
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