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common/usb/serial: add some trace logging.

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This commit is contained in:
Dario Nieuwenhuis 2022-03-07 00:24:13 +01:00
parent 24b6478a7c
commit 88d9599a63
1 changed files with 26 additions and 6 deletions
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32
embassy-hal-common/src/usb/usb_serial.rs
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@ -167,6 +167,7 @@ impl<'bus, 'a, B: UsbBus> AsyncWrite for UsbSerial<'bus, 'a, B> {
let write_buf = this.write_buf.push_buf();
if write_buf.is_empty() {
trace!("buf full, registering waker");
this.write_waker.register(cx.waker());
return Poll::Pending;
}
@ -244,10 +245,18 @@ impl<'bus, 'a, B: UsbBus> UsbSerial<'bus, 'a, B> {
};
if !buf.is_empty() {
trace!("writing packet len {}", buf.len());
let count = match self.inner.write_packet(buf) {
Ok(c) => c,
Err(UsbError::WouldBlock) => 0,
Ok(c) => {
trace!("write packet: OK {}", c);
c
}
Err(UsbError::WouldBlock) => {
trace!("write packet: WouldBlock");
0
}
Err(_) => {
trace!("write packet: error");
self.write_error = true;
return;
}
@ -260,11 +269,20 @@ impl<'bus, 'a, B: UsbBus> UsbSerial<'bus, 'a, B> {
}
self.write_buf.pop(count);
} else if full_size_packets > 0 {
if let Err(e) = self.inner.write_packet(&[]) {
if !matches!(e, UsbError::WouldBlock) {
self.write_error = true;
trace!("writing empty packet");
match self.inner.write_packet(&[]) {
Ok(_) => {
trace!("write empty packet: OK");
}
Err(UsbError::WouldBlock) => {
trace!("write empty packet: WouldBlock");
return;
}
Err(_) => {
trace!("write empty packet: Error");
self.write_error = true;
return;
}
return;
}
self.write_state = WriteState::Idle;
}
@ -287,7 +305,9 @@ where
}
fn endpoint_in_complete(&mut self, addr: EndpointAddress) {
trace!("DONE endpoint_in_complete");
if addr == self.inner.write_ep_address() {
trace!("DONE writing packet, waking");
self.write_waker.wake();
self.flush_write();