Merge pull request #2528 from caleb-garrett/hash
STM32 Hash Accelerator
This commit is contained in:
Dario Nieuwenhuis
GitHub
commit
8c82d1bcbc
9 changed files with 701 additions and 11 deletions
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@ -1056,6 +1056,7 @@ fn main() {
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(("dac", "CH1"), quote!(crate::dac::DacDma1)),
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(("dac", "CH2"), quote!(crate::dac::DacDma2)),
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(("timer", "UP"), quote!(crate::timer::UpDma)),
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(("hash", "IN"), quote!(crate::hash::Dma)),
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(("timer", "CH1"), quote!(crate::timer::Ch1Dma)),
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(("timer", "CH2"), quote!(crate::timer::Ch2Dma)),
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(("timer", "CH3"), quote!(crate::timer::Ch3Dma)),
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545
embassy-stm32/src/hash/mod.rs
Normal file
545
embassy-stm32/src/hash/mod.rs
Normal file
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@ -0,0 +1,545 @@
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//! Hash generator (HASH)
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use core::cmp::min;
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#[cfg(hash_v2)]
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use core::future::poll_fn;
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use core::marker::PhantomData;
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#[cfg(hash_v2)]
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use core::ptr;
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#[cfg(hash_v2)]
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use core::task::Poll;
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use embassy_hal_internal::{into_ref, PeripheralRef};
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use embassy_sync::waitqueue::AtomicWaker;
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use stm32_metapac::hash::regs::*;
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use crate::dma::NoDma;
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#[cfg(hash_v2)]
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use crate::dma::Transfer;
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use crate::interrupt::typelevel::Interrupt;
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use crate::peripherals::HASH;
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use crate::rcc::sealed::RccPeripheral;
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use crate::{interrupt, pac, peripherals, Peripheral};
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#[cfg(hash_v1)]
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const NUM_CONTEXT_REGS: usize = 51;
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#[cfg(hash_v3)]
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const NUM_CONTEXT_REGS: usize = 103;
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#[cfg(any(hash_v2, hash_v4))]
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const NUM_CONTEXT_REGS: usize = 54;
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const HASH_BUFFER_LEN: usize = 132;
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const DIGEST_BLOCK_SIZE: usize = 128;
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static HASH_WAKER: AtomicWaker = AtomicWaker::new();
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/// HASH interrupt handler.
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pub struct InterruptHandler<T: Instance> {
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_phantom: PhantomData<T>,
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}
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impl<T: Instance> interrupt::typelevel::Handler<T::Interrupt> for InterruptHandler<T> {
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unsafe fn on_interrupt() {
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let bits = T::regs().sr().read();
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if bits.dinis() {
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T::regs().imr().modify(|reg| reg.set_dinie(false));
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HASH_WAKER.wake();
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}
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if bits.dcis() {
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T::regs().imr().modify(|reg| reg.set_dcie(false));
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HASH_WAKER.wake();
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}
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}
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}
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///Hash algorithm selection
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#[derive(Clone, Copy, PartialEq)]
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pub enum Algorithm {
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/// SHA-1 Algorithm
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SHA1 = 0,
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#[cfg(any(hash_v1, hash_v2, hash_v4))]
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/// MD5 Algorithm
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MD5 = 1,
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/// SHA-224 Algorithm
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SHA224 = 2,
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/// SHA-256 Algorithm
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SHA256 = 3,
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#[cfg(hash_v3)]
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/// SHA-384 Algorithm
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SHA384 = 12,
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#[cfg(hash_v3)]
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/// SHA-512/224 Algorithm
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SHA512_224 = 13,
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#[cfg(hash_v3)]
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/// SHA-512/256 Algorithm
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SHA512_256 = 14,
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#[cfg(hash_v3)]
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/// SHA-256 Algorithm
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SHA512 = 15,
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}
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/// Input data width selection
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#[repr(u8)]
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#[derive(Clone, Copy)]
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pub enum DataType {
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///32-bit data, no data is swapped.
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Width32 = 0,
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///16-bit data, each half-word is swapped.
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Width16 = 1,
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///8-bit data, all bytes are swapped.
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Width8 = 2,
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///1-bit data, all bits are swapped.
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Width1 = 3,
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}
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/// Stores the state of the HASH peripheral for suspending/resuming
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/// digest calculation.
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pub struct Context {
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first_word_sent: bool,
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buffer: [u8; HASH_BUFFER_LEN],
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buflen: usize,
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algo: Algorithm,
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format: DataType,
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imr: u32,
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str: u32,
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cr: u32,
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csr: [u32; NUM_CONTEXT_REGS],
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}
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/// HASH driver.
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pub struct Hash<'d, T: Instance, D = NoDma> {
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_peripheral: PeripheralRef<'d, T>,
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#[allow(dead_code)]
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dma: PeripheralRef<'d, D>,
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}
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impl<'d, T: Instance, D> Hash<'d, T, D> {
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/// Instantiates, resets, and enables the HASH peripheral.
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pub fn new(
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peripheral: impl Peripheral<P = T> + 'd,
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dma: impl Peripheral<P = D> + 'd,
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_irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
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) -> Self {
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HASH::enable_and_reset();
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into_ref!(peripheral, dma);
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let instance = Self {
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_peripheral: peripheral,
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dma: dma,
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};
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T::Interrupt::unpend();
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unsafe { T::Interrupt::enable() };
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instance
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}
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/// Starts computation of a new hash and returns the saved peripheral state.
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pub fn start(&mut self, algorithm: Algorithm, format: DataType) -> Context {
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// Define a context for this new computation.
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let mut ctx = Context {
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first_word_sent: false,
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buffer: [0; HASH_BUFFER_LEN],
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buflen: 0,
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algo: algorithm,
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format: format,
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imr: 0,
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str: 0,
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cr: 0,
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csr: [0; NUM_CONTEXT_REGS],
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};
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// Set the data type in the peripheral.
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T::regs().cr().modify(|w| w.set_datatype(ctx.format as u8));
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// Select the algorithm.
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#[cfg(hash_v1)]
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if ctx.algo == Algorithm::MD5 {
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T::regs().cr().modify(|w| w.set_algo(true));
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}
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#[cfg(hash_v2)]
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{
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// Select the algorithm.
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let mut algo0 = false;
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let mut algo1 = false;
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if ctx.algo == Algorithm::MD5 || ctx.algo == Algorithm::SHA256 {
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algo0 = true;
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}
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if ctx.algo == Algorithm::SHA224 || ctx.algo == Algorithm::SHA256 {
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algo1 = true;
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}
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T::regs().cr().modify(|w| w.set_algo0(algo0));
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T::regs().cr().modify(|w| w.set_algo1(algo1));
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}
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#[cfg(any(hash_v3, hash_v4))]
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T::regs().cr().modify(|w| w.set_algo(ctx.algo as u8));
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T::regs().cr().modify(|w| w.set_init(true));
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// Store and return the state of the peripheral.
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self.store_context(&mut ctx);
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ctx
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}
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/// Restores the peripheral state using the given context,
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/// then updates the state with the provided data.
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/// Peripheral state is saved upon return.
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pub fn update_blocking(&mut self, ctx: &mut Context, input: &[u8]) {
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let mut data_waiting = input.len() + ctx.buflen;
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if data_waiting < DIGEST_BLOCK_SIZE || (data_waiting < ctx.buffer.len() && !ctx.first_word_sent) {
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// There isn't enough data to digest a block, so append it to the buffer.
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ctx.buffer[ctx.buflen..ctx.buflen + input.len()].copy_from_slice(input);
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ctx.buflen += input.len();
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return;
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}
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// Restore the peripheral state.
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self.load_context(&ctx);
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let mut ilen_remaining = input.len();
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let mut input_start = 0;
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// Handle first block.
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if !ctx.first_word_sent {
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let empty_len = ctx.buffer.len() - ctx.buflen;
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let copy_len = min(empty_len, ilen_remaining);
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// Fill the buffer.
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if copy_len > 0 {
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ctx.buffer[ctx.buflen..ctx.buflen + copy_len].copy_from_slice(&input[0..copy_len]);
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ctx.buflen += copy_len;
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ilen_remaining -= copy_len;
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input_start += copy_len;
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}
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self.accumulate_blocking(ctx.buffer.as_slice());
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data_waiting -= ctx.buflen;
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ctx.buflen = 0;
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ctx.first_word_sent = true;
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}
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if data_waiting < DIGEST_BLOCK_SIZE {
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// There isn't enough data remaining to process another block, so store it.
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ctx.buffer[0..ilen_remaining].copy_from_slice(&input[input_start..input_start + ilen_remaining]);
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ctx.buflen += ilen_remaining;
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} else {
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// First ingest the data in the buffer.
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let empty_len = DIGEST_BLOCK_SIZE - ctx.buflen;
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if empty_len > 0 {
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let copy_len = min(empty_len, ilen_remaining);
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ctx.buffer[ctx.buflen..ctx.buflen + copy_len]
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.copy_from_slice(&input[input_start..input_start + copy_len]);
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ctx.buflen += copy_len;
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ilen_remaining -= copy_len;
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input_start += copy_len;
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}
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self.accumulate_blocking(&ctx.buffer[0..DIGEST_BLOCK_SIZE]);
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ctx.buflen = 0;
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// Move any extra data to the now-empty buffer.
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let leftovers = ilen_remaining % 64;
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if leftovers > 0 {
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ctx.buffer[0..leftovers].copy_from_slice(&input[input.len() - leftovers..input.len()]);
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ctx.buflen += leftovers;
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ilen_remaining -= leftovers;
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}
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// Hash the remaining data.
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self.accumulate_blocking(&input[input_start..input_start + ilen_remaining]);
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}
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// Save the peripheral context.
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self.store_context(ctx);
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}
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/// Restores the peripheral state using the given context,
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/// then updates the state with the provided data.
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/// Peripheral state is saved upon return.
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#[cfg(hash_v2)]
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pub async fn update(&mut self, ctx: &mut Context, input: &[u8])
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where
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D: crate::hash::Dma<T>,
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{
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let data_waiting = input.len() + ctx.buflen;
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if data_waiting < DIGEST_BLOCK_SIZE {
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// There isn't enough data to digest a block, so append it to the buffer.
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ctx.buffer[ctx.buflen..ctx.buflen + input.len()].copy_from_slice(input);
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ctx.buflen += input.len();
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return;
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}
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// Restore the peripheral state.
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self.load_context(&ctx);
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// Enable multiple DMA transfers.
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T::regs().cr().modify(|w| w.set_mdmat(true));
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let mut ilen_remaining = input.len();
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let mut input_start = 0;
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// First ingest the data in the buffer.
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let empty_len = DIGEST_BLOCK_SIZE - ctx.buflen;
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if empty_len > 0 {
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let copy_len = min(empty_len, ilen_remaining);
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ctx.buffer[ctx.buflen..ctx.buflen + copy_len].copy_from_slice(&input[input_start..input_start + copy_len]);
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ctx.buflen += copy_len;
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ilen_remaining -= copy_len;
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input_start += copy_len;
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}
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self.accumulate(&ctx.buffer[..DIGEST_BLOCK_SIZE]).await;
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ctx.buflen = 0;
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// Move any extra data to the now-empty buffer.
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let leftovers = ilen_remaining % DIGEST_BLOCK_SIZE;
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if leftovers > 0 {
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assert!(ilen_remaining >= leftovers);
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ctx.buffer[0..leftovers].copy_from_slice(&input[input.len() - leftovers..input.len()]);
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ctx.buflen += leftovers;
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ilen_remaining -= leftovers;
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} else {
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ctx.buffer
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.copy_from_slice(&input[input.len() - DIGEST_BLOCK_SIZE..input.len()]);
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ctx.buflen += DIGEST_BLOCK_SIZE;
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ilen_remaining -= DIGEST_BLOCK_SIZE;
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}
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// Hash the remaining data.
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self.accumulate(&input[input_start..input_start + ilen_remaining]).await;
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// Save the peripheral context.
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self.store_context(ctx);
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}
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/// Computes a digest for the given context.
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/// The digest buffer must be large enough to accomodate a digest for the selected algorithm.
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/// The largest returned digest size is 128 bytes for SHA-512.
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/// Panics if the supplied digest buffer is too short.
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pub fn finish_blocking(&mut self, mut ctx: Context, digest: &mut [u8]) -> usize {
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// Restore the peripheral state.
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self.load_context(&ctx);
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// Hash the leftover bytes, if any.
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self.accumulate_blocking(&ctx.buffer[0..ctx.buflen]);
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ctx.buflen = 0;
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//Start the digest calculation.
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T::regs().str().write(|w| w.set_dcal(true));
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// Block waiting for digest.
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while !T::regs().sr().read().dcis() {}
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// Return the digest.
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let digest_words = match ctx.algo {
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Algorithm::SHA1 => 5,
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#[cfg(any(hash_v1, hash_v2, hash_v4))]
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Algorithm::MD5 => 4,
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Algorithm::SHA224 => 7,
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Algorithm::SHA256 => 8,
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#[cfg(hash_v3)]
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Algorithm::SHA384 => 12,
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#[cfg(hash_v3)]
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Algorithm::SHA512_224 => 7,
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#[cfg(hash_v3)]
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Algorithm::SHA512_256 => 8,
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#[cfg(hash_v3)]
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Algorithm::SHA512 => 16,
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};
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let digest_len_bytes = digest_words * 4;
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// Panics if the supplied digest buffer is too short.
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if digest.len() < digest_len_bytes {
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panic!("Digest buffer must be at least {} bytes long.", digest_words * 4);
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}
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let mut i = 0;
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while i < digest_words {
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let word = T::regs().hr(i).read();
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digest[(i * 4)..((i * 4) + 4)].copy_from_slice(word.to_be_bytes().as_slice());
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i += 1;
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}
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digest_len_bytes
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}
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/// Computes a digest for the given context.
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/// The digest buffer must be large enough to accomodate a digest for the selected algorithm.
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/// The largest returned digest size is 128 bytes for SHA-512.
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/// Panics if the supplied digest buffer is too short.
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#[cfg(hash_v2)]
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pub async fn finish(&mut self, mut ctx: Context, digest: &mut [u8]) -> usize
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where
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D: crate::hash::Dma<T>,
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{
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// Restore the peripheral state.
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self.load_context(&ctx);
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// Must be cleared prior to the last DMA transfer.
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T::regs().cr().modify(|w| w.set_mdmat(false));
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// Hash the leftover bytes, if any.
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self.accumulate(&ctx.buffer[0..ctx.buflen]).await;
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ctx.buflen = 0;
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// Wait for completion.
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poll_fn(|cx| {
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// Check if already done.
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let bits = T::regs().sr().read();
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if bits.dcis() {
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return Poll::Ready(());
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}
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// Register waker, then enable interrupts.
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HASH_WAKER.register(cx.waker());
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T::regs().imr().modify(|reg| reg.set_dcie(true));
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// Check for completion.
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let bits = T::regs().sr().read();
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if bits.dcis() {
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Poll::Ready(())
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} else {
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Poll::Pending
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}
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})
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.await;
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// Return the digest.
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let digest_words = match ctx.algo {
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Algorithm::SHA1 => 5,
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#[cfg(any(hash_v1, hash_v2, hash_v4))]
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Algorithm::MD5 => 4,
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Algorithm::SHA224 => 7,
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Algorithm::SHA256 => 8,
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#[cfg(hash_v3)]
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Algorithm::SHA384 => 12,
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#[cfg(hash_v3)]
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Algorithm::SHA512_224 => 7,
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#[cfg(hash_v3)]
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Algorithm::SHA512_256 => 8,
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#[cfg(hash_v3)]
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Algorithm::SHA512 => 16,
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};
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let digest_len_bytes = digest_words * 4;
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// Panics if the supplied digest buffer is too short.
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if digest.len() < digest_len_bytes {
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panic!("Digest buffer must be at least {} bytes long.", digest_words * 4);
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}
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let mut i = 0;
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while i < digest_words {
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let word = T::regs().hr(i).read();
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digest[(i * 4)..((i * 4) + 4)].copy_from_slice(word.to_be_bytes().as_slice());
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i += 1;
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}
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digest_len_bytes
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}
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/// Push data into the hash core.
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fn accumulate_blocking(&mut self, input: &[u8]) {
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// Set the number of valid bits.
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let num_valid_bits: u8 = (8 * (input.len() % 4)) as u8;
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T::regs().str().modify(|w| w.set_nblw(num_valid_bits));
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let mut i = 0;
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while i < input.len() {
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let mut word: [u8; 4] = [0; 4];
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let copy_idx = min(i + 4, input.len());
|
||||
word[0..copy_idx - i].copy_from_slice(&input[i..copy_idx]);
|
||||
T::regs().din().write_value(u32::from_ne_bytes(word));
|
||||
i += 4;
|
||||
}
|
||||
}
|
||||
|
||||
/// Push data into the hash core.
|
||||
#[cfg(hash_v2)]
|
||||
async fn accumulate(&mut self, input: &[u8])
|
||||
where
|
||||
D: crate::hash::Dma<T>,
|
||||
{
|
||||
// Ignore an input length of 0.
|
||||
if input.len() == 0 {
|
||||
return;
|
||||
}
|
||||
|
||||
// Set the number of valid bits.
|
||||
let num_valid_bits: u8 = (8 * (input.len() % 4)) as u8;
|
||||
T::regs().str().modify(|w| w.set_nblw(num_valid_bits));
|
||||
|
||||
// Configure DMA to transfer input to hash core.
|
||||
let dma_request = self.dma.request();
|
||||
let dst_ptr = T::regs().din().as_ptr();
|
||||
let mut num_words = input.len() / 4;
|
||||
if input.len() % 4 > 0 {
|
||||
num_words += 1;
|
||||
}
|
||||
let src_ptr = ptr::slice_from_raw_parts(input.as_ptr().cast(), num_words);
|
||||
let dma_transfer =
|
||||
unsafe { Transfer::new_write_raw(&mut self.dma, dma_request, src_ptr, dst_ptr, Default::default()) };
|
||||
T::regs().cr().modify(|w| w.set_dmae(true));
|
||||
|
||||
// Wait for the transfer to complete.
|
||||
dma_transfer.await;
|
||||
}
|
||||
|
||||
/// Save the peripheral state to a context.
|
||||
fn store_context(&mut self, ctx: &mut Context) {
|
||||
// Block waiting for data in ready.
|
||||
while !T::regs().sr().read().dinis() {}
|
||||
|
||||
// Store peripheral context.
|
||||
ctx.imr = T::regs().imr().read().0;
|
||||
ctx.str = T::regs().str().read().0;
|
||||
ctx.cr = T::regs().cr().read().0;
|
||||
let mut i = 0;
|
||||
while i < NUM_CONTEXT_REGS {
|
||||
ctx.csr[i] = T::regs().csr(i).read();
|
||||
i += 1;
|
||||
}
|
||||
}
|
||||
|
||||
/// Restore the peripheral state from a context.
|
||||
fn load_context(&mut self, ctx: &Context) {
|
||||
// Restore the peripheral state from the context.
|
||||
T::regs().imr().write_value(Imr { 0: ctx.imr });
|
||||
T::regs().str().write_value(Str { 0: ctx.str });
|
||||
T::regs().cr().write_value(Cr { 0: ctx.cr });
|
||||
T::regs().cr().modify(|w| w.set_init(true));
|
||||
let mut i = 0;
|
||||
while i < NUM_CONTEXT_REGS {
|
||||
T::regs().csr(i).write_value(ctx.csr[i]);
|
||||
i += 1;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
pub(crate) mod sealed {
|
||||
use super::*;
|
||||
|
||||
pub trait Instance {
|
||||
fn regs() -> pac::hash::Hash;
|
||||
}
|
||||
}
|
||||
|
||||
/// HASH instance trait.
|
||||
pub trait Instance: sealed::Instance + Peripheral<P = Self> + crate::rcc::RccPeripheral + 'static + Send {
|
||||
/// Interrupt for this HASH instance.
|
||||
type Interrupt: interrupt::typelevel::Interrupt;
|
||||
}
|
||||
|
||||
foreach_interrupt!(
|
||||
($inst:ident, hash, HASH, GLOBAL, $irq:ident) => {
|
||||
impl Instance for peripherals::$inst {
|
||||
type Interrupt = crate::interrupt::typelevel::$irq;
|
||||
}
|
||||
|
||||
impl sealed::Instance for peripherals::$inst {
|
||||
fn regs() -> crate::pac::hash::Hash {
|
||||
crate::pac::$inst
|
||||
}
|
||||
}
|
||||
};
|
||||
);
|
||||
|
||||
dma_trait!(Dma, Instance);
|
||||
|
|
@ -45,6 +45,8 @@ pub mod exti;
|
|||
pub mod flash;
|
||||
#[cfg(fmc)]
|
||||
pub mod fmc;
|
||||
#[cfg(hash)]
|
||||
pub mod hash;
|
||||
#[cfg(hrtim)]
|
||||
pub mod hrtim;
|
||||
#[cfg(i2c)]
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
[target.'cfg(all(target_arch = "arm", target_os = "none"))']
|
||||
# replace STM32F429ZITx with your chip as listed in `probe-rs chip list`
|
||||
runner = "probe-rs run --chip STM32F767ZITx"
|
||||
runner = "probe-rs run --chip STM32F777ZITx"
|
||||
|
||||
[build]
|
||||
target = "thumbv7em-none-eabihf"
|
||||
|
|
|
|||
|
|
@ -5,8 +5,8 @@ version = "0.1.0"
|
|||
license = "MIT OR Apache-2.0"
|
||||
|
||||
[dependencies]
|
||||
# Change stm32f767zi to your chip name, if necessary.
|
||||
embassy-stm32 = { version = "0.1.0", path = "../../embassy-stm32", features = ["defmt", "stm32f767zi", "memory-x", "unstable-pac", "time-driver-any", "exti"] }
|
||||
# Change stm32f777zi to your chip name, if necessary.
|
||||
embassy-stm32 = { version = "0.1.0", path = "../../embassy-stm32", features = ["defmt", "stm32f777zi", "memory-x", "unstable-pac", "time-driver-any", "exti"] }
|
||||
embassy-sync = { version = "0.5.0", path = "../../embassy-sync", features = ["defmt"] }
|
||||
embassy-executor = { version = "0.5.0", path = "../../embassy-executor", features = ["task-arena-size-32768", "arch-cortex-m", "executor-thread", "defmt", "integrated-timers"] }
|
||||
embassy-time = { version = "0.3.0", path = "../../embassy-time", features = ["defmt", "defmt-timestamp-uptime", "tick-hz-32_768"] }
|
||||
|
|
@ -28,6 +28,7 @@ rand_core = "0.6.3"
|
|||
critical-section = "1.1"
|
||||
embedded-storage = "0.3.1"
|
||||
static_cell = "2"
|
||||
sha2 = { version = "0.10.8", default-features = false }
|
||||
|
||||
[profile.release]
|
||||
debug = 2
|
||||
|
|
|
|||
|
|
@ -19,7 +19,7 @@ use {defmt_rtt as _, panic_probe as _};
|
|||
|
||||
bind_interrupts!(struct Irqs {
|
||||
ETH => eth::InterruptHandler;
|
||||
RNG => rng::InterruptHandler<peripherals::RNG>;
|
||||
HASH_RNG => rng::InterruptHandler<peripherals::RNG>;
|
||||
});
|
||||
|
||||
type Device = Ethernet<'static, ETH, GenericSMI>;
|
||||
|
|
|
|||
56
examples/stm32f7/src/bin/hash.rs
Normal file
56
examples/stm32f7/src/bin/hash.rs
Normal file
|
|
@ -0,0 +1,56 @@
|
|||
#![no_std]
|
||||
#![no_main]
|
||||
|
||||
use defmt::info;
|
||||
use embassy_executor::Spawner;
|
||||
use embassy_stm32::hash::*;
|
||||
use embassy_stm32::{bind_interrupts, hash, peripherals, Config};
|
||||
use embassy_time::Instant;
|
||||
use sha2::{Digest, Sha256};
|
||||
use {defmt_rtt as _, panic_probe as _};
|
||||
|
||||
bind_interrupts!(struct Irqs {
|
||||
HASH_RNG => hash::InterruptHandler<peripherals::HASH>;
|
||||
});
|
||||
|
||||
#[embassy_executor::main]
|
||||
async fn main(_spawner: Spawner) -> ! {
|
||||
let config = Config::default();
|
||||
let p = embassy_stm32::init(config);
|
||||
|
||||
let test_1: &[u8] = b"as;dfhaslfhas;oifvnasd;nifvnhasd;nifvhndlkfghsd;nvfnahssdfgsdafgsasdfasdfasdfasdfasdfghjklmnbvcalskdjghalskdjgfbaslkdjfgbalskdjgbalskdjbdfhsdfhsfghsfghfgh";
|
||||
let test_2: &[u8] = b"fdhalksdjfhlasdjkfhalskdjfhgal;skdjfgalskdhfjgalskdjfglafgadfgdfgdafgaadsfgfgdfgadrgsyfthxfgjfhklhjkfgukhulkvhlvhukgfhfsrghzdhxyfufynufyuszeradrtydyytserr";
|
||||
|
||||
let mut hw_hasher = Hash::new(p.HASH, p.DMA2_CH7, Irqs);
|
||||
|
||||
let hw_start_time = Instant::now();
|
||||
|
||||
// Compute a digest in hardware.
|
||||
let mut context = hw_hasher.start(Algorithm::SHA256, DataType::Width8);
|
||||
hw_hasher.update(&mut context, test_1).await;
|
||||
hw_hasher.update(&mut context, test_2).await;
|
||||
let mut hw_digest: [u8; 32] = [0; 32];
|
||||
hw_hasher.finish(context, &mut hw_digest).await;
|
||||
|
||||
let hw_end_time = Instant::now();
|
||||
let hw_execution_time = hw_end_time - hw_start_time;
|
||||
|
||||
let sw_start_time = Instant::now();
|
||||
|
||||
// Compute a digest in software.
|
||||
let mut sw_hasher = Sha256::new();
|
||||
sw_hasher.update(test_1);
|
||||
sw_hasher.update(test_2);
|
||||
let sw_digest = sw_hasher.finalize();
|
||||
|
||||
let sw_end_time = Instant::now();
|
||||
let sw_execution_time = sw_end_time - sw_start_time;
|
||||
|
||||
info!("Hardware Digest: {:?}", hw_digest);
|
||||
info!("Software Digest: {:?}", sw_digest[..]);
|
||||
info!("Hardware Execution Time: {:?}", hw_execution_time);
|
||||
info!("Software Execution Time: {:?}", sw_execution_time);
|
||||
assert_eq!(hw_digest, sw_digest[..]);
|
||||
|
||||
loop {}
|
||||
}
|
||||
|
|
@ -15,22 +15,23 @@ stm32f446re = ["embassy-stm32/stm32f446re", "chrono", "stop", "can", "not-gpdma"
|
|||
stm32f767zi = ["embassy-stm32/stm32f767zi", "chrono", "not-gpdma", "eth", "rng"]
|
||||
stm32g071rb = ["embassy-stm32/stm32g071rb", "cm0", "not-gpdma", "dac"]
|
||||
stm32g491re = ["embassy-stm32/stm32g491re", "chrono", "stop", "not-gpdma", "rng", "fdcan"]
|
||||
stm32h563zi = ["embassy-stm32/stm32h563zi", "chrono", "eth", "rng"]
|
||||
stm32h753zi = ["embassy-stm32/stm32h753zi", "chrono", "not-gpdma", "eth", "rng", "fdcan"]
|
||||
stm32h755zi = ["embassy-stm32/stm32h755zi-cm7", "chrono", "not-gpdma", "eth", "dac", "rng", "fdcan"]
|
||||
stm32h563zi = ["embassy-stm32/stm32h563zi", "chrono", "eth", "rng", "hash"]
|
||||
stm32h753zi = ["embassy-stm32/stm32h753zi", "chrono", "not-gpdma", "eth", "rng", "fdcan", "hash"]
|
||||
stm32h755zi = ["embassy-stm32/stm32h755zi-cm7", "chrono", "not-gpdma", "eth", "dac", "rng", "fdcan", "hash"]
|
||||
stm32h7a3zi = ["embassy-stm32/stm32h7a3zi", "not-gpdma", "rng", "fdcan"]
|
||||
stm32l073rz = ["embassy-stm32/stm32l073rz", "cm0", "not-gpdma", "rng"]
|
||||
stm32l152re = ["embassy-stm32/stm32l152re", "chrono", "not-gpdma"]
|
||||
stm32l496zg = ["embassy-stm32/stm32l496zg", "not-gpdma", "rng"]
|
||||
stm32l4a6zg = ["embassy-stm32/stm32l4a6zg", "chrono", "not-gpdma", "rng"]
|
||||
stm32l4a6zg = ["embassy-stm32/stm32l4a6zg", "chrono", "not-gpdma", "rng", "hash"]
|
||||
stm32l4r5zi = ["embassy-stm32/stm32l4r5zi", "chrono", "not-gpdma", "rng"]
|
||||
stm32l552ze = ["embassy-stm32/stm32l552ze", "not-gpdma", "rng"]
|
||||
stm32u585ai = ["embassy-stm32/stm32u585ai", "chrono", "rng"]
|
||||
stm32l552ze = ["embassy-stm32/stm32l552ze", "not-gpdma", "rng", "hash"]
|
||||
stm32u585ai = ["embassy-stm32/stm32u585ai", "chrono", "rng", "hash"]
|
||||
stm32u5a5zj = ["embassy-stm32/stm32u5a5zj", "chrono", "rng"]
|
||||
stm32wb55rg = ["embassy-stm32/stm32wb55rg", "chrono", "not-gpdma", "ble", "mac" , "rng"]
|
||||
stm32wba52cg = ["embassy-stm32/stm32wba52cg", "chrono", "rng"]
|
||||
stm32wba52cg = ["embassy-stm32/stm32wba52cg", "chrono", "rng", "hash"]
|
||||
stm32wl55jc = ["embassy-stm32/stm32wl55jc-cm4", "not-gpdma", "rng", "chrono"]
|
||||
|
||||
hash = []
|
||||
eth = ["embassy-executor/task-arena-size-16384"]
|
||||
rng = []
|
||||
sdmmc = []
|
||||
|
|
@ -74,6 +75,7 @@ static_cell = "2"
|
|||
portable-atomic = { version = "1.5", features = [] }
|
||||
|
||||
chrono = { version = "^0.4", default-features = false, optional = true}
|
||||
sha2 = { version = "0.10.8", default-features = false }
|
||||
|
||||
# BEGIN TESTS
|
||||
# Generated by gen_test.py. DO NOT EDIT.
|
||||
|
|
@ -107,6 +109,11 @@ name = "gpio"
|
|||
path = "src/bin/gpio.rs"
|
||||
required-features = []
|
||||
|
||||
[[bin]]
|
||||
name = "hash"
|
||||
path = "src/bin/hash.rs"
|
||||
required-features = [ "hash",]
|
||||
|
||||
[[bin]]
|
||||
name = "rng"
|
||||
path = "src/bin/rng.rs"
|
||||
|
|
|
|||
78
tests/stm32/src/bin/hash.rs
Normal file
78
tests/stm32/src/bin/hash.rs
Normal file
|
|
@ -0,0 +1,78 @@
|
|||
// required-features: hash
|
||||
#![no_std]
|
||||
#![no_main]
|
||||
|
||||
#[path = "../common.rs"]
|
||||
mod common;
|
||||
use common::*;
|
||||
use embassy_executor::Spawner;
|
||||
use embassy_stm32::dma::NoDma;
|
||||
use embassy_stm32::hash::*;
|
||||
use embassy_stm32::{bind_interrupts, hash, peripherals};
|
||||
use sha2::{Digest, Sha224, Sha256};
|
||||
use {defmt_rtt as _, panic_probe as _};
|
||||
|
||||
#[cfg(any(feature = "stm32l4a6zg", feature = "stm32h755zi", feature = "stm32h753zi"))]
|
||||
bind_interrupts!(struct Irqs {
|
||||
HASH_RNG => hash::InterruptHandler<peripherals::HASH>;
|
||||
});
|
||||
|
||||
#[cfg(any(
|
||||
feature = "stm32wba52cg",
|
||||
feature = "stm32l552ze",
|
||||
feature = "stm32h563zi",
|
||||
feature = "stm32u5a5zj",
|
||||
feature = "stm32u585ai"
|
||||
))]
|
||||
bind_interrupts!(struct Irqs {
|
||||
HASH => hash::InterruptHandler<peripherals::HASH>;
|
||||
});
|
||||
|
||||
#[embassy_executor::main]
|
||||
async fn main(_spawner: Spawner) {
|
||||
let p: embassy_stm32::Peripherals = embassy_stm32::init(config());
|
||||
let mut hw_hasher = Hash::new(p.HASH, NoDma, Irqs);
|
||||
|
||||
let test_1: &[u8] = b"as;dfhaslfhas;oifvnasd;nifvnhasd;nifvhndlkfghsd;nvfnahssdfgsdafgsasdfasdfasdfasdfasdfghjklmnbvcalskdjghalskdjgfbaslkdjfgbalskdjgbalskdjbdfhsdfhsfghsfghfgh";
|
||||
let test_2: &[u8] = b"fdhalksdjfhlasdjkfhalskdjfhgal;skdjfgalskdhfjgalskdjfglafgadfgdfgdafgaadsfgfgdfgadrgsyfthxfgjfhklhjkfgukhulkvhlvhukgfhfsrghzdhxyfufynufyuszeradrtydyytserr";
|
||||
let test_3: &[u8] = b"a.ewtkluGWEBR.KAJRBTA,RMNRBG,FDMGB.kger.tkasjrbt.akrjtba.krjtba.ktmyna,nmbvtyliasd;gdrtba,sfvs.kgjzshd.gkbsr.tksejb.SDkfBSE.gkfgb>ESkfbSE>gkJSBESE>kbSE>fk";
|
||||
|
||||
// Start an SHA-256 digest.
|
||||
let mut sha256context = hw_hasher.start(Algorithm::SHA256, DataType::Width8);
|
||||
hw_hasher.update_blocking(&mut sha256context, test_1);
|
||||
|
||||
// Interrupt the SHA-256 digest to compute an SHA-224 digest.
|
||||
let mut sha224context = hw_hasher.start(Algorithm::SHA224, DataType::Width8);
|
||||
hw_hasher.update_blocking(&mut sha224context, test_3);
|
||||
let mut sha224_digest_buffer: [u8; 28] = [0; 28];
|
||||
let _ = hw_hasher.finish_blocking(sha224context, &mut sha224_digest_buffer);
|
||||
|
||||
// Finish the SHA-256 digest.
|
||||
hw_hasher.update_blocking(&mut sha256context, test_2);
|
||||
let mut sha256_digest_buffer: [u8; 32] = [0; 32];
|
||||
let _ = hw_hasher.finish_blocking(sha256context, &mut sha256_digest_buffer);
|
||||
|
||||
// Compute the SHA-256 digest in software.
|
||||
let mut sw_sha256_hasher = Sha256::new();
|
||||
sw_sha256_hasher.update(test_1);
|
||||
sw_sha256_hasher.update(test_2);
|
||||
let sw_sha256_digest = sw_sha256_hasher.finalize();
|
||||
|
||||
//Compute the SHA-224 digest in software.
|
||||
let mut sw_sha224_hasher = Sha224::new();
|
||||
sw_sha224_hasher.update(test_3);
|
||||
let sw_sha224_digest = sw_sha224_hasher.finalize();
|
||||
|
||||
// Compare the SHA-256 digests.
|
||||
info!("Hardware SHA-256 Digest: {:?}", sha256_digest_buffer);
|
||||
info!("Software SHA-256 Digest: {:?}", sw_sha256_digest[..]);
|
||||
defmt::assert!(sha256_digest_buffer == sw_sha256_digest[..]);
|
||||
|
||||
// Compare the SHA-224 digests.
|
||||
info!("Hardware SHA-256 Digest: {:?}", sha224_digest_buffer);
|
||||
info!("Software SHA-256 Digest: {:?}", sw_sha224_digest[..]);
|
||||
defmt::assert!(sha224_digest_buffer == sw_sha224_digest[..]);
|
||||
|
||||
info!("Test OK");
|
||||
cortex_m::asm::bkpt();
|
||||
}
|
||||
Loading…
Reference in a new issue