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Merge #663

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663: stm32: Spi bugfixes r=Dirbaio a=GrantM11235



Co-authored-by: Grant Miller <GrantM11235@gmail.com>
This commit is contained in:
bors[bot] 2022-03-14 23:25:02 +00:00 • committed by GitHub
commit 8ef8ab1707
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GPG key ID: 4AEE18F83AFDEB23
1 changed files with 18 additions and 9 deletions
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27
embassy-stm32/src/spi/mod.rs
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@ -7,7 +7,7 @@ use embassy_hal_common::unborrow;
use futures::future::join; use futures::future::join;
use self::sealed::WordSize; use self::sealed::WordSize;
use crate::dma::{slice_ptr_parts, slice_ptr_parts_mut, NoDma, Transfer}; use crate::dma::{NoDma, Transfer};
use crate::gpio::sealed::{AFType, Pin as _}; use crate::gpio::sealed::{AFType, Pin as _};
use crate::gpio::AnyPin; use crate::gpio::AnyPin;
use crate::pac::spi::Spi as Regs; use crate::pac::spi::Spi as Regs;
@ -411,6 +411,10 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
where where
Tx: TxDma<T>, Tx: TxDma<T>,
{ {
if data.len() == 0 {
return Ok(());
}
self.set_word_size(W::WORDSIZE); self.set_word_size(W::WORDSIZE);
unsafe { unsafe {
T::REGS.cr1().modify(|w| { T::REGS.cr1().modify(|w| {
@ -418,10 +422,6 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
}); });
} }
// TODO: This is unnecessary in some versions because
// clearing SPE automatically clears the fifos
flush_rx_fifo(T::REGS);
let tx_request = self.txdma.request(); let tx_request = self.txdma.request();
let tx_dst = T::REGS.tx_ptr(); let tx_dst = T::REGS.tx_ptr();
unsafe { self.txdma.start_write(tx_request, data, tx_dst) } unsafe { self.txdma.start_write(tx_request, data, tx_dst) }
@ -440,6 +440,9 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
tx_f.await; tx_f.await;
// flush here otherwise `finish_dma` hangs waiting for the rx fifo to empty
flush_rx_fifo(T::REGS);
finish_dma(T::REGS); finish_dma(T::REGS);
Ok(()) Ok(())
@ -450,6 +453,10 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
Tx: TxDma<T>, Tx: TxDma<T>,
Rx: RxDma<T>, Rx: RxDma<T>,
{ {
if data.len() == 0 {
return Ok(());
}
self.set_word_size(W::WORDSIZE); self.set_word_size(W::WORDSIZE);
unsafe { unsafe {
T::REGS.cr1().modify(|w| { T::REGS.cr1().modify(|w| {
@ -458,7 +465,7 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
set_rxdmaen(T::REGS, true); set_rxdmaen(T::REGS, true);
} }
let (_, clock_byte_count) = slice_ptr_parts_mut(data); let clock_byte_count = data.len();
let rx_request = self.rxdma.request(); let rx_request = self.rxdma.request();
let rx_src = T::REGS.rx_ptr(); let rx_src = T::REGS.rx_ptr();
@ -499,9 +506,11 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
Tx: TxDma<T>, Tx: TxDma<T>,
Rx: RxDma<T>, Rx: RxDma<T>,
{ {
let (_, rx_len) = slice_ptr_parts(read); assert_eq!(read.len(), write.len());
let (_, tx_len) = slice_ptr_parts(write);
assert_eq!(rx_len, tx_len); if read.len() == 0 {
return Ok(());
}
self.set_word_size(W::WORDSIZE); self.set_word_size(W::WORDSIZE);
unsafe { unsafe {