Merge #716
716: Implement giant (chunked) DMA transfers r=Dirbaio a=matoushybl There is a breaking change in the Channel trait in the method `remaining_transfers()`, this method however hasn't been used anywhere in the codebase and the return type changed from u16 to u32, so all of the previous use cases should work. Co-authored-by: Matous Hybl <hyblmatous@gmail.com>
This commit is contained in:
commit
97e24b0568
5 changed files with 333 additions and 13 deletions
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@ -379,7 +379,23 @@ where
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/// This method starts the capture and finishes when both the dma transfer and DCMI finish the frame transfer.
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/// The implication is that the input buffer size must be exactly the size of the captured frame.
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///
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/// Note that when `buffer.len() > 0xffff` the capture future requires some real-time guarantees to be upheld
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/// (must be polled fast enough so the buffers get switched before data is overwritten).
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/// It is therefore recommended that it is run on higher priority executor.
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pub async fn capture(&mut self, buffer: &mut [u32]) -> Result<(), Error> {
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if buffer.len() <= 0xffff {
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return self.capture_small(buffer).await;
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} else {
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#[cfg(feature = "unsafe-double-buffered-dma")]
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return self.capture_giant(buffer).await;
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#[cfg(not(feature = "unsafe-double-buffered-dma"))]
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panic!("For DCMI transfers with length > 0xffff, the `unsafe-double-buffered-dma` must be enabled.");
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}
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}
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async fn capture_small(&mut self, buffer: &mut [u32]) -> Result<(), Error> {
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let channel = &mut self.dma;
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let request = channel.request();
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@ -428,6 +444,122 @@ where
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result
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}
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#[cfg(feature = "unsafe-double-buffered-dma")]
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async fn capture_giant(&mut self, buffer: &mut [u32]) -> Result<(), Error> {
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use crate::dma::TransferOptions;
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let data_len = buffer.len();
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let chunk_estimate = data_len / 0xffff;
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let mut chunks = chunk_estimate + 1;
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while data_len % chunks != 0 {
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chunks += 1;
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}
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let chunk_size = data_len / chunks;
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let mut remaining_chunks = chunks - 2;
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let mut m0ar = buffer.as_mut_ptr();
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let mut m1ar = unsafe { buffer.as_mut_ptr().add(chunk_size) };
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let channel = &mut self.dma;
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let request = channel.request();
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let r = self.inner.regs();
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let src = r.dr().ptr() as *mut u32;
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unsafe {
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channel.start_double_buffered_read(
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request,
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src,
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m0ar,
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m1ar,
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chunk_size,
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TransferOptions::default(),
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);
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}
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let mut last_chunk_set_for_transfer = false;
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let mut buffer0_last_accessible = false;
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let dma_result = poll_fn(|cx| {
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channel.set_waker(cx.waker());
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let buffer0_currently_accessible = unsafe { channel.is_buffer0_accessible() };
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// check if the accessible buffer changed since last poll
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if buffer0_last_accessible == buffer0_currently_accessible {
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return Poll::Pending;
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}
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buffer0_last_accessible = !buffer0_last_accessible;
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if remaining_chunks != 0 {
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if remaining_chunks % 2 == 0 && buffer0_currently_accessible {
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m0ar = unsafe { m0ar.add(2 * chunk_size) };
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unsafe { channel.set_buffer0(m0ar) }
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remaining_chunks -= 1;
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} else if !buffer0_currently_accessible {
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m1ar = unsafe { m1ar.add(2 * chunk_size) };
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unsafe { channel.set_buffer1(m1ar) };
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remaining_chunks -= 1;
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}
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} else {
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if buffer0_currently_accessible {
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unsafe { channel.set_buffer0(buffer.as_mut_ptr()) }
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} else {
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unsafe { channel.set_buffer1(buffer.as_mut_ptr()) }
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}
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if last_chunk_set_for_transfer {
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channel.request_stop();
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return Poll::Ready(());
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}
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last_chunk_set_for_transfer = true;
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}
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Poll::Pending
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});
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Self::clear_interrupt_flags();
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Self::enable_irqs();
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let result = poll_fn(|cx| {
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STATE.waker.register(cx.waker());
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let ris = unsafe { crate::pac::DCMI.ris().read() };
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if ris.err_ris() {
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unsafe {
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crate::pac::DCMI.icr().write(|r| {
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r.set_err_isc(true);
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})
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};
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Poll::Ready(Err(Error::PeripheralError))
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} else if ris.ovr_ris() {
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unsafe {
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crate::pac::DCMI.icr().write(|r| {
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r.set_ovr_isc(true);
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})
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};
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Poll::Ready(Err(Error::Overrun))
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} else if ris.frame_ris() {
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unsafe {
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crate::pac::DCMI.icr().write(|r| {
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r.set_frame_isc(true);
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})
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};
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Poll::Ready(Ok(()))
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} else {
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Poll::Pending
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}
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});
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unsafe { Self::toggle(true) };
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let (_, result) = futures::future::join(dma_result, result).await;
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unsafe { Self::toggle(false) };
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result
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}
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}
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mod sealed {
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@ -76,7 +76,6 @@ foreach_dma_channel! {
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);
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}
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unsafe fn start_write_repeated<W: Word>(&mut self, _request: Request, repeated: W, count: usize, reg_addr: *mut W, options: TransferOptions) {
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let buf = [repeated];
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low_level_api::start_transfer(
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@ -119,6 +118,30 @@ foreach_dma_channel! {
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);
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}
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unsafe fn start_double_buffered_read<W: super::Word>(
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&mut self,
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_request: Request,
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_reg_addr: *const W,
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_buffer0: *mut W,
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_buffer1: *mut W,
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_buffer_len: usize,
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_options: TransferOptions,
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) {
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panic!("Unsafe double buffered mode is unavailable on BDMA");
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}
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unsafe fn set_buffer0<W: super::Word>(&mut self, _buffer: *mut W) {
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panic!("Unsafe double buffered mode is unavailable on BDMA");
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}
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unsafe fn set_buffer1<W: super::Word>(&mut self, _buffer: *mut W) {
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panic!("Unsafe double buffered mode is unavailable on BDMA");
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}
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unsafe fn is_buffer0_accessible(&mut self) -> bool {
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panic!("Unsafe double buffered mode is unavailable on BDMA");
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}
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fn request_stop(&mut self){
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unsafe {low_level_api::request_stop(pac::$dma_peri, $channel_num);}
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}
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@ -232,7 +255,7 @@ mod low_level_api {
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// get a handle on the channel itself
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let ch = dma.ch(ch as _);
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// read the remaining transfer count. If this is zero, the transfer completed fully.
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ch.ndtr().read().ndt()
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ch.ndtr().read().ndt() as u16
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}
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/// Sets the waker for the specified DMA channel
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@ -41,15 +41,27 @@ impl From<FlowControl> for vals::Pfctrl {
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}
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}
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struct ChannelState {
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waker: AtomicWaker,
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}
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impl ChannelState {
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const fn new() -> Self {
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Self {
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waker: AtomicWaker::new(),
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}
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}
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}
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struct State {
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ch_wakers: [AtomicWaker; DMA_CHANNEL_COUNT],
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channels: [ChannelState; DMA_CHANNEL_COUNT],
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}
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impl State {
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const fn new() -> Self {
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const AW: AtomicWaker = AtomicWaker::new();
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const CH: ChannelState = ChannelState::new();
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Self {
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ch_wakers: [AW; DMA_CHANNEL_COUNT],
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channels: [CH; DMA_CHANNEL_COUNT],
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}
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}
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}
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@ -129,6 +141,46 @@ foreach_dma_channel! {
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);
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}
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unsafe fn start_double_buffered_read<W: Word>(
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&mut self,
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request: Request,
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reg_addr: *const W,
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buffer0: *mut W,
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buffer1: *mut W,
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buffer_len: usize,
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options: TransferOptions,
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) {
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low_level_api::start_dbm_transfer(
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pac::$dma_peri,
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$channel_num,
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request,
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vals::Dir::PERIPHERALTOMEMORY,
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reg_addr as *const u32,
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buffer0 as *mut u32,
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buffer1 as *mut u32,
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buffer_len,
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true,
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vals::Size::from(W::bits()),
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options,
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#[cfg(dmamux)]
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<Self as super::dmamux::sealed::MuxChannel>::DMAMUX_REGS,
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#[cfg(dmamux)]
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<Self as super::dmamux::sealed::MuxChannel>::DMAMUX_CH_NUM,
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);
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}
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unsafe fn set_buffer0<W: Word>(&mut self, buffer: *mut W) {
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low_level_api::set_dbm_buffer0(pac::$dma_peri, $channel_num, buffer as *mut u32);
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}
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unsafe fn set_buffer1<W: Word>(&mut self, buffer: *mut W) {
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low_level_api::set_dbm_buffer1(pac::$dma_peri, $channel_num, buffer as *mut u32);
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}
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unsafe fn is_buffer0_accessible(&mut self) -> bool {
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low_level_api::is_buffer0_accessible(pac::$dma_peri, $channel_num)
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}
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fn request_stop(&mut self) {
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unsafe {low_level_api::request_stop(pac::$dma_peri, $channel_num);}
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}
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@ -151,7 +203,6 @@ foreach_dma_channel! {
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}
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}
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}
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impl crate::dma::Channel for crate::peripherals::$channel_peri { }
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};
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}
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@ -212,6 +263,94 @@ mod low_level_api {
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});
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}
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pub unsafe fn start_dbm_transfer(
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dma: pac::dma::Dma,
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channel_number: u8,
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request: Request,
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dir: vals::Dir,
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peri_addr: *const u32,
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mem0_addr: *mut u32,
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mem1_addr: *mut u32,
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mem_len: usize,
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incr_mem: bool,
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data_size: vals::Size,
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options: TransferOptions,
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#[cfg(dmamux)] dmamux_regs: pac::dmamux::Dmamux,
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#[cfg(dmamux)] dmamux_ch_num: u8,
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) {
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#[cfg(dmamux)]
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super::super::dmamux::configure_dmamux(dmamux_regs, dmamux_ch_num, request);
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trace!(
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"Starting DBM transfer with 0: 0x{:x}, 1: 0x{:x}, len: 0x{:x}",
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mem0_addr as u32,
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mem1_addr as u32,
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mem_len
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);
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// "Preceding reads and writes cannot be moved past subsequent writes."
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fence(Ordering::SeqCst);
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reset_status(dma, channel_number);
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let ch = dma.st(channel_number as _);
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ch.par().write_value(peri_addr as u32);
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ch.m0ar().write_value(mem0_addr as u32);
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// configures the second buffer for DBM
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ch.m1ar().write_value(mem1_addr as u32);
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ch.ndtr().write_value(regs::Ndtr(mem_len as _));
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ch.cr().write(|w| {
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w.set_dir(dir);
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w.set_msize(data_size);
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w.set_psize(data_size);
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w.set_pl(vals::Pl::VERYHIGH);
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if incr_mem {
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w.set_minc(vals::Inc::INCREMENTED);
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} else {
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w.set_minc(vals::Inc::FIXED);
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}
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w.set_pinc(vals::Inc::FIXED);
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w.set_teie(true);
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w.set_tcie(true);
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#[cfg(dma_v1)]
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w.set_trbuff(true);
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#[cfg(dma_v2)]
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w.set_chsel(request);
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// enable double buffered mode
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w.set_dbm(vals::Dbm::ENABLED);
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w.set_pburst(options.pburst.into());
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w.set_mburst(options.mburst.into());
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w.set_pfctrl(options.flow_ctrl.into());
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w.set_en(true);
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});
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}
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pub unsafe fn set_dbm_buffer0(dma: pac::dma::Dma, channel_number: u8, mem_addr: *mut u32) {
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// get a handle on the channel itself
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let ch = dma.st(channel_number as _);
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// change M0AR to the new address
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ch.m0ar().write_value(mem_addr as _);
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}
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pub unsafe fn set_dbm_buffer1(dma: pac::dma::Dma, channel_number: u8, mem_addr: *mut u32) {
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// get a handle on the channel itself
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let ch = dma.st(channel_number as _);
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// change M1AR to the new address
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ch.m1ar().write_value(mem_addr as _);
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}
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pub unsafe fn is_buffer0_accessible(dma: pac::dma::Dma, channel_number: u8) -> bool {
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// get a handle on the channel itself
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let ch = dma.st(channel_number as _);
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// check the current target register value
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ch.cr().read().ct() == vals::Ct::MEMORY1
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}
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/// Stops the DMA channel.
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pub unsafe fn request_stop(dma: pac::dma::Dma, channel_number: u8) {
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// get a handle on the channel itself
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@ -246,7 +385,7 @@ mod low_level_api {
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/// Sets the waker for the specified DMA channel
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pub unsafe fn set_waker(state_number: usize, waker: &Waker) {
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STATE.ch_wakers[state_number].register(waker);
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STATE.channels[state_number].waker.register(waker);
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}
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pub unsafe fn reset_status(dma: pac::dma::Dma, channel_number: u8) {
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@ -260,9 +399,9 @@ mod low_level_api {
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}
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/// Safety: Must be called with a matching set of parameters for a valid dma channel
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pub unsafe fn on_irq_inner(dma: pac::dma::Dma, channel_num: u8, index: u8) {
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pub unsafe fn on_irq_inner(dma: pac::dma::Dma, channel_num: u8, state_index: u8) {
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let channel_num = channel_num as usize;
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let index = index as usize;
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let state_index = state_index as usize;
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let cr = dma.st(channel_num).cr();
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let isr = dma.isr(channel_num / 4).read();
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|
@ -273,9 +412,16 @@ mod low_level_api {
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dma.0 as u32, channel_num
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);
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}
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if isr.tcif(channel_num % 4) && cr.read().tcie() {
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cr.write(|_| ()); // Disable channel interrupts with the default value.
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STATE.ch_wakers[index].wake();
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if cr.read().dbm() == vals::Dbm::DISABLED {
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cr.write(|_| ()); // Disable channel with the default value.
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} else {
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// for double buffered mode, clear TCIF flag but do not stop the transfer
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dma.ifcr(channel_num / 4)
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.write(|w| w.set_tcif(channel_num % 4, true));
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}
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STATE.channels[state_index].waker.wake();
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}
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}
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}
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|
|
|
@ -76,6 +76,25 @@ pub(crate) mod sealed {
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options: TransferOptions,
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);
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/// DMA double-buffered mode is unsafe as UB can happen when the hardware writes to a buffer currently owned by the software
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/// more information can be found here: https://github.com/embassy-rs/embassy/issues/702
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/// This feature is now used solely for the purposes of implementing giant DMA transfers required for DCMI
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unsafe fn start_double_buffered_read<W: super::Word>(
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&mut self,
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request: Request,
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reg_addr: *const W,
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buffer0: *mut W,
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buffer1: *mut W,
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buffer_len: usize,
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options: TransferOptions,
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);
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unsafe fn set_buffer0<W: super::Word>(&mut self, buffer: *mut W);
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unsafe fn set_buffer1<W: super::Word>(&mut self, buffer: *mut W);
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unsafe fn is_buffer0_accessible(&mut self) -> bool;
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/// Requests the channel to stop.
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/// NOTE: The channel does not immediately stop, you have to wait
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/// for `is_running() = false`.
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|
|
|
@ -1,5 +1,5 @@
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MEMORY
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{
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FLASH : ORIGIN = 0x8000000, LENGTH = 1024K
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RAM : ORIGIN = 0x24000000, LENGTH = 128K
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}
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RAM : ORIGIN = 0x24000000, LENGTH = 384K
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}
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