Merge pull request #14 from timokroeger/uarte-power-optimization
UARTE power optimization and improvements
This commit is contained in:
commit
9bb4c97dc2
3 changed files with 91 additions and 42 deletions
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@ -17,8 +17,8 @@ use crate::hal::gpio::Port as GpioPort;
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use crate::hal::pac;
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use crate::hal::pac;
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use crate::hal::prelude::*;
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use crate::hal::prelude::*;
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use crate::hal::target_constants::EASY_DMA_SIZE;
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use crate::hal::target_constants::EASY_DMA_SIZE;
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use crate::interrupt;
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use crate::interrupt::OwnedInterrupt;
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use crate::interrupt::OwnedInterrupt;
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use crate::{interrupt, util};
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pub use crate::hal::uarte::Pins;
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pub use crate::hal::uarte::Pins;
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// Re-export SVD variants to allow user to directly set values.
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// Re-export SVD variants to allow user to directly set values.
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@ -131,6 +131,8 @@ where
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}
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}
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pub fn free(self) -> (T, T::Interrupt, Pins) {
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pub fn free(self) -> (T, T::Interrupt, Pins) {
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// Wait for the peripheral to be disabled from the ISR.
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while self.instance.enable.read().enable().is_enabled() {}
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(self.instance, self.irq, self.pins)
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(self.instance, self.irq, self.pins)
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}
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}
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@ -156,6 +158,13 @@ where
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uarte.events_endtx.reset();
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uarte.events_endtx.reset();
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trace!("endtx");
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trace!("endtx");
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compiler_fence(Ordering::SeqCst);
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compiler_fence(Ordering::SeqCst);
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if uarte.events_txstarted.read().bits() != 0 {
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// The ENDTX was signal triggered because DMA has finished.
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uarte.events_txstarted.reset();
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try_disable = true;
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}
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T::state().tx_done.signal(());
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T::state().tx_done.signal(());
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}
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}
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@ -170,6 +179,13 @@ where
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trace!("endrx");
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trace!("endrx");
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let len = uarte.rxd.amount.read().bits();
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let len = uarte.rxd.amount.read().bits();
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compiler_fence(Ordering::SeqCst);
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compiler_fence(Ordering::SeqCst);
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if uarte.events_rxstarted.read().bits() != 0 {
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// The ENDRX was signal triggered because DMA buffer is full.
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uarte.events_rxstarted.reset();
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try_disable = true;
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}
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T::state().rx_done.signal(len);
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T::state().rx_done.signal(len);
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}
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}
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@ -204,7 +220,7 @@ impl<T: Instance> embassy::uart::Uart for Uarte<T> {
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// `mem::forget()` on a previous future after polling it once.
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// `mem::forget()` on a previous future after polling it once.
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assert!(!self.tx_started());
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assert!(!self.tx_started());
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self.enable();
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T::state().tx_done.reset();
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SendFuture {
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SendFuture {
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uarte: self,
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uarte: self,
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@ -227,7 +243,7 @@ impl<T: Instance> embassy::uart::Uart for Uarte<T> {
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// `mem::forget()` on a previous future after polling it once.
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// `mem::forget()` on a previous future after polling it once.
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assert!(!self.rx_started());
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assert!(!self.rx_started());
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self.enable();
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T::state().rx_done.reset();
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ReceiveFuture {
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ReceiveFuture {
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uarte: self,
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uarte: self,
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@ -241,7 +257,7 @@ pub struct SendFuture<'a, T>
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where
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where
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T: Instance,
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T: Instance,
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{
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{
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uarte: &'a Uarte<T>,
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uarte: &'a mut Uarte<T>,
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buf: &'a [u8],
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buf: &'a [u8],
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}
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}
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@ -259,7 +275,9 @@ where
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.instance
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.instance
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.tasks_stoptx
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.tasks_stoptx
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.write(|w| unsafe { w.bits(1) });
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.write(|w| unsafe { w.bits(1) });
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T::state().tx_done.blocking_wait();
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// TX is stopped almost instantly, spinning is fine.
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while !T::state().tx_done.signaled() {}
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}
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}
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}
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}
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}
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}
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@ -273,28 +291,34 @@ where
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fn poll(self: core::pin::Pin<&mut Self>, cx: &mut Context<'_>) -> Poll<Self::Output> {
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fn poll(self: core::pin::Pin<&mut Self>, cx: &mut Context<'_>) -> Poll<Self::Output> {
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let Self { uarte, buf } = unsafe { self.get_unchecked_mut() };
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let Self { uarte, buf } = unsafe { self.get_unchecked_mut() };
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if !uarte.tx_started() {
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if T::state().tx_done.poll_wait(cx).is_pending() {
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let uarte = &uarte.instance;
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T::state().tx_done.reset();
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let ptr = buf.as_ptr();
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let ptr = buf.as_ptr();
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let len = buf.len();
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let len = buf.len();
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assert!(len <= EASY_DMA_SIZE);
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assert!(len <= EASY_DMA_SIZE);
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// TODO: panic if buffer is not in SRAM
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// TODO: panic if buffer is not in SRAM
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uarte.enable();
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compiler_fence(Ordering::SeqCst);
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compiler_fence(Ordering::SeqCst);
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uarte.txd.ptr.write(|w| unsafe { w.ptr().bits(ptr as u32) });
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uarte
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uarte
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.instance
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.txd
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.ptr
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.write(|w| unsafe { w.ptr().bits(ptr as u32) });
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uarte
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.instance
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.txd
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.txd
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.maxcnt
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.maxcnt
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.write(|w| unsafe { w.maxcnt().bits(len as _) });
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.write(|w| unsafe { w.maxcnt().bits(len as _) });
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trace!("starttx");
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trace!("starttx");
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uarte.tasks_starttx.write(|w| unsafe { w.bits(1) });
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uarte.instance.tasks_starttx.write(|w| unsafe { w.bits(1) });
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}
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while !uarte.tx_started() {} // Make sure transmission has started
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T::state().tx_done.poll_wait(cx).map(|()| Ok(()))
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Poll::Pending
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} else {
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Poll::Ready(Ok(()))
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}
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}
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}
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}
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}
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@ -303,7 +327,7 @@ pub struct ReceiveFuture<'a, T>
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where
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where
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T: Instance,
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T: Instance,
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{
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{
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uarte: &'a Uarte<T>,
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uarte: &'a mut Uarte<T>,
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buf: &'a mut [u8],
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buf: &'a mut [u8],
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}
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}
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@ -313,14 +337,15 @@ where
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{
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{
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fn drop(self: &mut Self) {
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fn drop(self: &mut Self) {
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if self.uarte.rx_started() {
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if self.uarte.rx_started() {
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trace!("stoprx");
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trace!("stoprx (drop)");
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self.uarte.instance.events_rxstarted.reset();
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self.uarte.instance.events_rxstarted.reset();
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self.uarte
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self.uarte
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.instance
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.instance
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.tasks_stoprx
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.tasks_stoprx
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.write(|w| unsafe { w.bits(1) });
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.write(|w| unsafe { w.bits(1) });
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T::state().rx_done.blocking_wait();
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util::low_power_wait_until(|| T::state().rx_done.signaled())
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}
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}
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}
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}
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}
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}
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@ -334,27 +359,35 @@ where
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fn poll(self: core::pin::Pin<&mut Self>, cx: &mut Context<'_>) -> Poll<Self::Output> {
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fn poll(self: core::pin::Pin<&mut Self>, cx: &mut Context<'_>) -> Poll<Self::Output> {
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let Self { uarte, buf } = unsafe { self.get_unchecked_mut() };
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let Self { uarte, buf } = unsafe { self.get_unchecked_mut() };
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if !uarte.rx_started() {
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match T::state().rx_done.poll_wait(cx) {
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let uarte = &uarte.instance;
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Poll::Pending if !uarte.rx_started() => {
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let ptr = buf.as_ptr();
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let len = buf.len();
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assert!(len <= EASY_DMA_SIZE);
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T::state().rx_done.reset();
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uarte.enable();
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let ptr = buf.as_ptr();
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compiler_fence(Ordering::SeqCst);
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let len = buf.len();
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uarte
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assert!(len <= EASY_DMA_SIZE);
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.instance
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.rxd
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.ptr
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.write(|w| unsafe { w.ptr().bits(ptr as u32) });
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uarte
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.instance
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.rxd
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.maxcnt
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.write(|w| unsafe { w.maxcnt().bits(len as _) });
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compiler_fence(Ordering::SeqCst);
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trace!("startrx");
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uarte.rxd.ptr.write(|w| unsafe { w.ptr().bits(ptr as u32) });
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uarte.instance.tasks_startrx.write(|w| unsafe { w.bits(1) });
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uarte
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while !uarte.rx_started() {} // Make sure reception has started
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.rxd
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.maxcnt
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.write(|w| unsafe { w.maxcnt().bits(len as _) });
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trace!("startrx");
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Poll::Pending
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uarte.tasks_startrx.write(|w| unsafe { w.bits(1) });
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}
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Poll::Pending => Poll::Pending,
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Poll::Ready(_) => Poll::Ready(Ok(())),
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}
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}
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T::state().rx_done.poll_wait(cx).map(|_| Ok(()))
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}
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}
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}
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}
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@ -365,8 +398,19 @@ where
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{
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{
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/// Stops the ongoing reception and returns the number of bytes received.
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/// Stops the ongoing reception and returns the number of bytes received.
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pub async fn stop(self) -> usize {
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pub async fn stop(self) -> usize {
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drop(self);
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let len = if self.uarte.rx_started() {
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let len = T::state().rx_done.wait().await;
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trace!("stoprx (stop)");
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self.uarte.instance.events_rxstarted.reset();
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self.uarte
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.instance
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.tasks_stoprx
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.write(|w| unsafe { w.bits(1) });
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T::state().rx_done.wait().await
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} else {
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// Transfer was stopped before it even started. No bytes were sent.
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0
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};
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len as _
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len as _
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}
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}
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}
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}
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@ -1,2 +1,12 @@
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pub mod peripheral;
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pub mod peripheral;
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pub mod ring_buffer;
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pub mod ring_buffer;
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/// Low power blocking wait loop using WFE/SEV.
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pub fn low_power_wait_until(mut condition: impl FnMut() -> bool) {
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while !condition() {
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// WFE might "eat" an event that would have otherwise woken the executor.
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cortex_m::asm::wfe();
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}
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// Retrigger an event to be transparent to the executor.
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cortex_m::asm::sev();
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}
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@ -63,12 +63,7 @@ impl<T: Send> Signal<T> {
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futures::future::poll_fn(move |cx| self.poll_wait(cx))
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futures::future::poll_fn(move |cx| self.poll_wait(cx))
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}
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}
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/// Blocks until the signal has been received.
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pub fn signaled(&self) -> bool {
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///
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cortex_m::interrupt::free(|_| matches!(unsafe { &*self.state.get() }, State::Signaled(_)))
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/// Returns immediately when [`poll_wait()`] has not been called before.
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pub fn blocking_wait(&self) {
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while cortex_m::interrupt::free(|_| {
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matches!(unsafe { &*self.state.get() }, State::Waiting(_))
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}) {}
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}
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}
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}
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}
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