implement generics on serial
This commit is contained in:
xoviat
parent
bd3deb785a
commit
9bcb0c36dc
2 changed files with 152 additions and 81 deletions
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@ -14,6 +14,7 @@ use embassy::traits::uart::Uart;
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use embassy::util::Forever;
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use embassy_stm32f4::interrupt;
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use embassy_stm32f4::serial;
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use stm32f4xx_hal::dma::StreamsTuple;
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use stm32f4xx_hal::prelude::*;
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use stm32f4xx_hal::serial::config::Config;
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use stm32f4xx_hal::stm32;
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@ -38,10 +39,12 @@ async fn run(dp: stm32::Peripherals, _cp: cortex_m::Peripherals) {
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.pclk1(24.mhz())
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.freeze();
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let streams = StreamsTuple::new(dp.DMA2);
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let mut serial = unsafe {
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serial::Serial::new(
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dp.USART1,
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dp.DMA2,
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(streams.7, streams.2),
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(
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gpioa.pa9.into_alternate_af7(),
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gpioa.pa10.into_alternate_af7(),
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@ -53,6 +56,24 @@ async fn run(dp: stm32::Peripherals, _cp: cortex_m::Peripherals) {
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clocks,
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)
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};
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let streams = StreamsTuple::new(dp.DMA1);
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let mut serial = unsafe {
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serial::Serial::new(
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dp.USART2,
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(streams.6, streams.5),
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(
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gpioa.pa2.into_alternate_af7(),
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gpioa.pa3.into_alternate_af7(),
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),
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interrupt::take!(DMA1_STREAM6),
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interrupt::take!(DMA1_STREAM5),
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interrupt::take!(USART2),
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Config::default().baudrate(9600.bps()),
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clocks,
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)
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};
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let buf = singleton!(: [u8; 30] = [0; 30]).unwrap();
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buf[5] = 0x01;
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@ -8,129 +8,120 @@ use core::future::Future;
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use core::ptr;
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use core::sync::atomic::{self, Ordering};
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use embassy::interrupt::InterruptExt;
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use embassy::interrupt::{Interrupt, InterruptExt};
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use embassy::traits::uart::{Error, Uart};
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use embassy::util::Signal;
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use embassy::util::InterruptFuture;
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use crate::hal::dma;
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use crate::hal::dma::config::DmaConfig;
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use crate::hal::dma::traits::{PeriAddress, Stream};
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use crate::hal::dma::{Stream2, Stream7, StreamsTuple, Transfer};
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use crate::hal::dma::{MemoryToPeripheral, PeripheralToMemory, Transfer};
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use crate::hal::rcc::Clocks;
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use crate::hal::serial;
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use crate::hal::serial::config::{Config as SerialConfig, DmaConfig as SerialDmaConfig};
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use crate::hal::serial::Pins;
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use crate::hal::serial::{Event as SerialEvent, Serial as HalSerial};
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use crate::interrupt;
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use crate::pac::{DMA2, USART1};
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use crate::pac;
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/// Interface to the Serial peripheral
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pub struct Serial<USART: PeriAddress<MemSize = u8>, TSTREAM: Stream, RSTREAM: Stream> {
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pub struct Serial<
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USART: PeriAddress<MemSize = u8>,
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TSTREAM: Stream,
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RSTREAM: Stream,
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CHANNEL: dma::traits::Channel,
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TINT: Interrupt,
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RINT: Interrupt,
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UINT: Interrupt,
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> {
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tx_stream: Option<TSTREAM>,
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rx_stream: Option<RSTREAM>,
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usart: Option<USART>,
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tx_int: interrupt::DMA2_STREAM7,
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rx_int: interrupt::DMA2_STREAM2,
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usart_int: interrupt::USART1,
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tx_int: TINT,
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rx_int: RINT,
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usart_int: UINT,
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channel: core::marker::PhantomData<CHANNEL>,
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}
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struct State {
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tx_int: Signal<()>,
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rx_int: Signal<()>,
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}
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// static mut INSTANCE: *const Serial<USART1, Stream7<DMA2>, Stream2<DMA2>> = ptr::null_mut();
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static STATE: State = State {
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tx_int: Signal::new(),
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rx_int: Signal::new(),
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};
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static mut INSTANCE: *const Serial<USART1, Stream7<DMA2>, Stream2<DMA2>> = ptr::null_mut();
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impl Serial<USART1, Stream7<DMA2>, Stream2<DMA2>> {
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impl<USART, TSTREAM, RSTREAM, CHANNEL, TINT, RINT, UINT>
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Serial<USART, TSTREAM, RSTREAM, CHANNEL, TINT, RINT, UINT>
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where
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USART: serial::Instance
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+ dma::traits::PeriAddress<MemSize = u8>
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+ dma::traits::DMASet<TSTREAM, CHANNEL, MemoryToPeripheral>
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+ dma::traits::DMASet<RSTREAM, CHANNEL, PeripheralToMemory>
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+ WithInterrupt<Instance = UINT>,
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TSTREAM: Stream + WithInterrupt<Instance = TINT>,
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RSTREAM: Stream + WithInterrupt<Instance = RINT>,
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CHANNEL: dma::traits::Channel,
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TINT: Interrupt,
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RINT: Interrupt,
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UINT: Interrupt,
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{
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// Leaking futures is forbidden!
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pub unsafe fn new<PINS>(
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usart: USART1,
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dma: DMA2,
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usart: USART,
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streams: (TSTREAM, RSTREAM),
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pins: PINS,
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tx_int: interrupt::DMA2_STREAM7,
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rx_int: interrupt::DMA2_STREAM2,
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usart_int: interrupt::USART1,
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tx_int: TINT,
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rx_int: RINT,
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usart_int: UINT,
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mut config: SerialConfig,
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clocks: Clocks,
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) -> Self
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where
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PINS: Pins<USART1>,
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PINS: Pins<USART>,
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{
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config.dma = SerialDmaConfig::TxRx;
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let mut serial = HalSerial::usart1(usart, pins, config, clocks).unwrap();
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let mut serial = HalSerial::new(usart, pins, config, clocks).unwrap();
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serial.listen(SerialEvent::Idle);
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// serial.listen(SerialEvent::Txe);
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let (usart, _) = serial.release();
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// Register ISR
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tx_int.set_handler(Self::on_tx_irq);
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rx_int.set_handler(Self::on_rx_irq);
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usart_int.set_handler(Self::on_rx_irq);
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// usart_int.unpend();
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// usart_int.enable();
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let streams = StreamsTuple::new(dma);
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let (tx_stream, rx_stream) = streams;
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Serial {
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tx_stream: Some(streams.7),
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rx_stream: Some(streams.2),
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tx_stream: Some(tx_stream),
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rx_stream: Some(rx_stream),
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usart: Some(usart),
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tx_int: tx_int,
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rx_int: rx_int,
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usart_int: usart_int,
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channel: core::marker::PhantomData,
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}
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}
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unsafe fn on_tx_irq(_ctx: *mut ()) {
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let s = &(*INSTANCE);
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s.tx_int.disable();
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STATE.tx_int.signal(());
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}
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unsafe fn on_rx_irq(_ctx: *mut ()) {
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let s = &(*INSTANCE);
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atomic::compiler_fence(Ordering::Acquire);
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s.rx_int.disable();
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s.usart_int.disable();
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atomic::compiler_fence(Ordering::Release);
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STATE.rx_int.signal(());
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}
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unsafe fn on_usart_irq(_ctx: *mut ()) {
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let s = &(*INSTANCE);
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atomic::compiler_fence(Ordering::Acquire);
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s.rx_int.disable();
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s.usart_int.disable();
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atomic::compiler_fence(Ordering::Release);
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STATE.rx_int.signal(());
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}
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}
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impl Uart for Serial<USART1, Stream7<DMA2>, Stream2<DMA2>> {
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impl<USART, TSTREAM, RSTREAM, CHANNEL, TINT, RINT, UINT> Uart
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for Serial<USART, TSTREAM, RSTREAM, CHANNEL, TINT, RINT, UINT>
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where
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USART: serial::Instance
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+ dma::traits::PeriAddress<MemSize = u8>
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+ dma::traits::DMASet<TSTREAM, CHANNEL, MemoryToPeripheral>
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+ dma::traits::DMASet<RSTREAM, CHANNEL, PeripheralToMemory>
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+ WithInterrupt<Instance = UINT>
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+ 'static,
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TSTREAM: Stream + WithInterrupt<Instance = TINT> + 'static,
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RSTREAM: Stream + WithInterrupt<Instance = RINT> + 'static,
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CHANNEL: dma::traits::Channel + 'static,
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TINT: Interrupt + 'static,
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RINT: Interrupt + 'static,
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UINT: Interrupt + 'static,
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{
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type SendFuture<'a> = impl Future<Output = Result<(), Error>> + 'a;
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type ReceiveFuture<'a> = impl Future<Output = Result<(), Error>> + 'a;
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/// Sends serial data.
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fn send<'a>(&'a mut self, buf: &'a [u8]) -> Self::SendFuture<'a> {
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unsafe { INSTANCE = self };
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#[allow(mutable_transmutes)]
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let static_buf = unsafe { core::mem::transmute::<&'a [u8], &'static mut [u8]>(buf) };
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let tx_stream = self.tx_stream.take().unwrap();
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let usart = self.usart.take().unwrap();
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STATE.tx_int.reset();
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async move {
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let mut tx_transfer = Transfer::init(
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@ -144,11 +135,11 @@ impl Uart for Serial<USART1, Stream7<DMA2>, Stream2<DMA2>> {
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.double_buffer(false),
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);
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self.tx_int.unpend();
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self.tx_int.enable();
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let fut = InterruptFuture::new(&mut self.tx_int);
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tx_transfer.start(|_usart| {});
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STATE.tx_int.wait().await;
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fut.await;
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let (tx_stream, usart, _buf, _) = tx_transfer.free();
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self.tx_stream.replace(tx_stream);
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@ -165,12 +156,11 @@ impl Uart for Serial<USART1, Stream7<DMA2>, Stream2<DMA2>> {
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/// unfinished transfers after a timeout to prevent lockup when no more data
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/// is incoming.
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fn receive<'a>(&'a mut self, buf: &'a mut [u8]) -> Self::ReceiveFuture<'a> {
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unsafe { INSTANCE = self };
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let static_buf = unsafe { core::mem::transmute::<&'a mut [u8], &'static mut [u8]>(buf) };
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let rx_stream = self.rx_stream.take().unwrap();
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let usart = self.usart.take().unwrap();
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STATE.rx_int.reset();
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async move {
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let mut rx_transfer = Transfer::init(
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rx_stream,
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@ -182,14 +172,74 @@ impl Uart for Serial<USART1, Stream7<DMA2>, Stream2<DMA2>> {
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.memory_increment(true)
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.double_buffer(false),
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);
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self.rx_int.unpend();
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self.rx_int.enable();
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let fut = InterruptFuture::new(&mut self.rx_int);
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rx_transfer.start(|_usart| {});
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STATE.rx_int.wait().await;
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fut.await;
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let (rx_stream, usart, _, _) = rx_transfer.free();
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self.rx_stream.replace(rx_stream);
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self.usart.replace(usart);
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Ok(())
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}
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}
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}
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mod private {
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pub trait Sealed {}
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}
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pub trait WithInterrupt: private::Sealed {
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type Instance;
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}
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macro_rules! dma {
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($($PER:ident => ($dma:ident, $stream:ident),)+) => {
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$(
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impl private::Sealed for dma::$stream<pac::$dma> {}
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impl WithInterrupt for dma::$stream<pac::$dma> {
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type Instance = interrupt::$PER;
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}
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)+
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}
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}
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macro_rules! usart {
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($($PER:ident => ($usart:ident),)+) => {
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$(
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impl private::Sealed for pac::$usart {}
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impl WithInterrupt for pac::$usart {
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type Instance = interrupt::$PER;
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}
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)+
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}
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}
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dma! {
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DMA2_STREAM0 => (DMA2, Stream0),
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DMA2_STREAM1 => (DMA2, Stream1),
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DMA2_STREAM2 => (DMA2, Stream2),
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DMA2_STREAM3 => (DMA2, Stream3),
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DMA2_STREAM4 => (DMA2, Stream4),
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DMA2_STREAM5 => (DMA2, Stream5),
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DMA2_STREAM6 => (DMA2, Stream6),
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DMA2_STREAM7 => (DMA2, Stream7),
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DMA1_STREAM0 => (DMA1, Stream0),
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DMA1_STREAM1 => (DMA1, Stream1),
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DMA1_STREAM2 => (DMA1, Stream2),
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DMA1_STREAM3 => (DMA1, Stream3),
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DMA1_STREAM4 => (DMA1, Stream4),
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DMA1_STREAM5 => (DMA1, Stream5),
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DMA1_STREAM6 => (DMA1, Stream6),
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}
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usart! {
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USART1 => (USART1),
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USART2 => (USART2),
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USART3 => (USART3),
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UART4 => (UART4),
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UART5 => (UART5),
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USART6 => (USART6),
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}
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