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Update stm32-data

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This commit is contained in:
Dario Nieuwenhuis 2022-02-07 20:40:35 +01:00
parent 965e3c436e
commit aaf25bbac3
3 changed files with 16 additions and 29 deletions
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2
stm32-data

@ -1 +1 @@
Subproject commit 69ac5bce28972de33b57497454421c6ac862b0ed Subproject commit fe221f48442d4b6eef6dcfd04d9d4deec4402cce

20
stm32-metapac-gen/src/data.rs
View file

@ -1,5 +1,4 @@
use serde::Deserialize; use serde::Deserialize;
use std::collections::HashMap;
#[derive(Debug, Eq, PartialEq, Clone, Deserialize)] #[derive(Debug, Eq, PartialEq, Clone, Deserialize)]
pub struct Chip { pub struct Chip {
@ -7,21 +6,24 @@ pub struct Chip {
pub family: String, pub family: String,
pub line: String, pub line: String,
pub cores: Vec<Core>, pub cores: Vec<Core>,
pub flash: Memory, pub memory: Vec<MemoryRegion>,
pub ram: Memory,
pub packages: Vec<Package>, pub packages: Vec<Package>,
} }
#[derive(Debug, Eq, PartialEq, Clone, Deserialize)] #[derive(Debug, Eq, PartialEq, Clone, Deserialize)]
pub struct Memory { pub struct MemoryRegion {
pub bytes: u32, pub name: String,
pub regions: HashMap<String, MemoryRegion>, pub kind: MemoryRegionKind,
pub address: u32,
pub size: u32,
} }
#[derive(Debug, Eq, PartialEq, Clone, Deserialize)] #[derive(Debug, Eq, PartialEq, Clone, Deserialize)]
pub struct MemoryRegion { pub enum MemoryRegionKind {
pub base: u32, #[serde(rename = "flash")]
pub bytes: Option<u32>, Flash,
#[serde(rename = "ram")]
Ram,
} }
#[derive(Debug, Eq, PartialEq, Clone, Deserialize)] #[derive(Debug, Eq, PartialEq, Clone, Deserialize)]

23
stm32-metapac-gen/src/lib.rs
View file

@ -587,35 +587,20 @@ fn bytes_find(haystack: &[u8], needle: &[u8]) -> Option<usize> {
fn gen_memory_x(out_dir: &PathBuf, chip: &Chip) { fn gen_memory_x(out_dir: &PathBuf, chip: &Chip) {
let mut memory_x = String::new(); let mut memory_x = String::new();
let flash_bytes = chip let flash = chip.memory.iter().find(|r| r.name == "BANK_1").unwrap();
.flash let ram = chip.memory.iter().find(|r| r.name == "SRAM").unwrap();
.regions
.get("BANK_1")
.unwrap()
.bytes
.unwrap_or(chip.flash.bytes);
let flash_origin = chip.flash.regions.get("BANK_1").unwrap().base;
let ram_bytes = chip
.ram
.regions
.get("SRAM")
.unwrap()
.bytes
.unwrap_or(chip.ram.bytes);
let ram_origin = chip.ram.regions.get("SRAM").unwrap().base;
write!(memory_x, "MEMORY\n{{\n").unwrap(); write!(memory_x, "MEMORY\n{{\n").unwrap();
write!( write!(
memory_x, memory_x,
" FLASH : ORIGIN = 0x{:x}, LENGTH = {}\n", " FLASH : ORIGIN = 0x{:x}, LENGTH = {}\n",
flash_origin, flash_bytes flash.address, flash.size,
) )
.unwrap(); .unwrap();
write!( write!(
memory_x, memory_x,
" RAM : ORIGIN = 0x{:x}, LENGTH = {}\n", " RAM : ORIGIN = 0x{:x}, LENGTH = {}\n",
ram_origin, ram_bytes ram.address, ram.size,
) )
.unwrap(); .unwrap();
write!(memory_x, "}}").unwrap(); write!(memory_x, "}}").unwrap();