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Delay setting TX buffer mode until user had a chance to configure it.

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This commit is contained in:
Corey Schuhen 2024-03-02 09:45:30 +10:00
parent 9e403fa89a
commit bf06d10534
2 changed files with 9 additions and 7 deletions
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4
embassy-stm32/src/can/fd/config.rs
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@ -290,9 +290,9 @@ impl Default for GlobalFilter {
/// TX buffer operation mode
#[derive(Clone, Copy, PartialEq, Eq, Debug)]
pub enum TxBufferMode {
/// TX FIFO operation
/// TX FIFO operation - In this mode CAN frames are trasmitted strictly in write order.
Fifo,
/// TX queue operation
/// TX queue operation - In this mode CAN frames are transmitted according to CAN priority.
Queue,
}

12
embassy-stm32/src/can/fd/peripheral.rs
View file

@ -307,11 +307,6 @@ impl Registers {
"Error reading endianness test value from FDCAN core"
);
// Framework specific settings are set here
// set TxBuffer Mode
self.regs.txbc().write(|w| w.set_tfqm(_config.tx_buffer_mode.into()));
// set standard filters list size to 28
// set extended filters list size to 8
// REQUIRED: we use the memory map as if these settings are set
@ -357,6 +352,7 @@ impl Registers {
/// Applies the settings of a new FdCanConfig See [`FdCanConfig`]
#[inline]
pub fn apply_config(&mut self, config: FdCanConfig) {
self.set_tx_buffer_mode(config.tx_buffer_mode);
self.set_data_bit_timing(config.dbtr);
self.set_nominal_bit_timing(config.nbtr);
self.set_automatic_retransmit(config.automatic_retransmit);
@ -504,6 +500,12 @@ impl Registers {
self.regs.cccr().modify(|w| w.set_efbi(enabled));
}
/// Configures TX Buffer Mode
#[inline]
pub fn set_tx_buffer_mode(&mut self, tbm: TxBufferMode) {
self.regs.txbc().write(|w| w.set_tfqm(tbm.into()));
}
/// Configures frame transmission mode. See
/// [`FdCanConfig::set_frame_transmit`]
#[inline]