rustfmt
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56b345c722
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d28ba1d606
1 changed files with 21 additions and 14 deletions
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@ -204,14 +204,13 @@ impl Default for Config {
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// ensure ADC is not out of range by default even if APB2 is maxxed out (36mhz)
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adc_pre: ADCPrescaler::DIV6,
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#[cfg(all(stm32f3, not(rcc_f37)))]
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adc: AdcClockSource::Hclk(AdcHclkPrescaler::Div1),
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#[cfg(all(stm32f3, not(rcc_f37), adc3_common))]
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adc34: AdcClockSource::Hclk(AdcHclkPrescaler::Div1),
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#[cfg(stm32f334)]
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hrtim: HrtimClockSource::BusClk,
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#[cfg(all(stm32f3, not(stm32f37)))]
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#[cfg(all(stm32f3, not(rcc_f37)))]
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tim: Default::default(),
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}
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}
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@ -450,33 +449,37 @@ pub(crate) unsafe fn init(config: Config) {
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#[cfg(all(stm32f3, not(rcc_f37)))]
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match config.tim.tim1 {
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TimClockSource::PClk2 => {},
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TimClockSource::PClk2 => {}
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TimClockSource::PllClk => {
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RCC.cfgr3().modify(|w| w.set_tim1sw(crate::pac::rcc::vals::Timsw::PLL1_P));
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RCC.cfgr3()
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.modify(|w| w.set_tim1sw(crate::pac::rcc::vals::Timsw::PLL1_P));
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}
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};
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#[cfg(any(all(stm32f303, any(package_D, package_E)), all(stm32f302, any(package_D, package_E))))]
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match config.tim.tim2 {
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TimClockSource::PClk2 => {},
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TimClockSource::PClk2 => {}
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TimClockSource::PllClk => {
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RCC.cfgr3().modify(|w| w.set_tim2sw(crate::pac::rcc::vals::Timsw::PLL1_P));
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RCC.cfgr3()
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.modify(|w| w.set_tim2sw(crate::pac::rcc::vals::Timsw::PLL1_P));
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}
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};
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#[cfg(any(all(stm32f303, any(package_D, package_E)), all(stm32f302, any(package_D, package_E))))]
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match config.tim.tim34 {
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TimClockSource::PClk2 => {},
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TimClockSource::PClk2 => {}
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TimClockSource::PllClk => {
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RCC.cfgr3().modify(|w| w.set_tim34sw(crate::pac::rcc::vals::Timsw::PLL1_P));
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RCC.cfgr3()
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.modify(|w| w.set_tim34sw(crate::pac::rcc::vals::Timsw::PLL1_P));
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}
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};
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#[cfg(any(all(stm32f303, any(package_B, package_C, package_D, package_E)), stm32f358))]
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match config.tim.tim8 {
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TimClockSource::PClk2 => {},
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TimClockSource::PClk2 => {}
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TimClockSource::PllClk => {
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RCC.cfgr3().modify(|w| w.set_tim8sw(crate::pac::rcc::vals::Timsw::PLL1_P));
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RCC.cfgr3()
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.modify(|w| w.set_tim8sw(crate::pac::rcc::vals::Timsw::PLL1_P));
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}
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};
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@ -489,7 +492,8 @@ pub(crate) unsafe fn init(config: Config) {
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match config.tim.tim15 {
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TimClockSource::PClk2 => None,
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TimClockSource::PllClk => {
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RCC.cfgr3().modify(|w| w.set_tim15sw(crate::pac::rcc::vals::Timsw::PLL1_P));
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RCC.cfgr3()
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.modify(|w| w.set_tim15sw(crate::pac::rcc::vals::Timsw::PLL1_P));
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}
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};
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@ -502,7 +506,8 @@ pub(crate) unsafe fn init(config: Config) {
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match config.tim.tim16 {
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TimClockSource::PClk2 => None,
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TimClockSource::PllClk => {
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RCC.cfgr3().modify(|w| w.set_tim16sw(crate::pac::rcc::vals::Timsw::PLL1_P));
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RCC.cfgr3()
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.modify(|w| w.set_tim16sw(crate::pac::rcc::vals::Timsw::PLL1_P));
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}
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};
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@ -515,7 +520,8 @@ pub(crate) unsafe fn init(config: Config) {
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match config.tim.tim17 {
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TimClockSource::PClk2 => None,
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TimClockSource::PllClk => {
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RCC.cfgr3().modify(|w| w.set_tim17sw(crate::pac::rcc::vals::Timsw::PLL1_P));
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RCC.cfgr3()
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.modify(|w| w.set_tim17sw(crate::pac::rcc::vals::Timsw::PLL1_P));
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}
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}
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@ -523,7 +529,8 @@ pub(crate) unsafe fn init(config: Config) {
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match config.tim.tim20 {
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TimClockSource::PClk2 => None,
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TimClockSource::PllClk => {
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RCC.cfgr3().modify(|w| w.set_tim20sw(crate::pac::rcc::vals::Timsw::PLL1_P));
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RCC.cfgr3()
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.modify(|w| w.set_tim20sw(crate::pac::rcc::vals::Timsw::PLL1_P));
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}
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}
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