NaxdyOrg/embassy
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity

rp/clocks: reset all plls at once

Browse source 
we might not configure both, so we should put the others into reset
state. leaving them fully as is might leave them running, which might
not be the goal for runtime reconfig (when it comes around). this now
mirrors how we reset all clock-using peripherals and only unreset those
that are properly clocked.
This commit is contained in:
pennae 2023-05-13 18:55:40 +02:00
parent 2f2860b096
commit d3494a4bdf
1 changed files with 7 additions and 10 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

17
embassy-rp/src/clocks.rs
View file

@ -203,6 +203,13 @@ pub(crate) unsafe fn init(config: ClockConfig) {
c.clk_ref_ctrl().modify(|w| w.set_src(ClkRefCtrlSrc::ROSC_CLKSRC_PH));
while c.clk_ref_selected().read() != 1 {}
// Reset the PLLs
let mut peris = reset::Peripherals(0);
peris.set_pll_sys(true);
peris.set_pll_usb(true);
reset::reset(peris);
reset::unreset_wait(peris);
if let Some(config) = config.rosc {
configure_rosc(config);
}
@ -587,16 +594,6 @@ unsafe fn configure_pll(p: pac::pll::Pll, input_freq: u32, config: PllConfig) {
assert!(config.post_div2 <= config.post_div1);
assert!(ref_freq <= (config.vco_freq / 16));
// Reset it
let mut peris = reset::Peripherals(0);
match p {
pac::PLL_SYS => peris.set_pll_sys(true),
pac::PLL_USB => peris.set_pll_usb(true),
_ => unreachable!(),
}
reset::reset(peris);
reset::unreset_wait(peris);
// Load VCO-related dividers before starting VCO
p.cs().write(|w| w.set_refdiv(config.refdiv as _));
p.fbdiv_int().write(|w| w.set_fbdiv_int(fbdiv as _));