This commit is contained in:
Henrik Alsér 2022-07-06 03:31:21 +02:00
parent 264b32d71b
commit d3d82ad87d
2 changed files with 60 additions and 45 deletions

View file

@ -1,67 +1,82 @@
//! Blocking shared I2C bus //! Blocking shared I2C bus
use core::cell::RefCell; use core::cell::RefCell;
use core::fmt::Debug;
use core::future::Future;
use embedded_hal_1::i2c; use embassy::blocking_mutex::raw::RawMutex;
use embassy::blocking_mutex::Mutex;
use embedded_hal_1::i2c::blocking::{I2c, Operation};
use embedded_hal_1::i2c::ErrorType;
#[derive(Copy, Clone, Eq, PartialEq, Debug)] use crate::shared_bus::i2c::I2cBusDeviceError;
pub enum I2cBusDeviceError<BUS> {
I2c(BUS), pub struct I2cBusDevice<'a, M: RawMutex, BUS> {
bus: &'a Mutex<M, RefCell<BUS>>,
} }
impl<BUS> i2c::Error for I2cBusDeviceError<BUS> impl<'a, M: RawMutex, BUS> I2cBusDevice<'a, M, BUS> {
where pub fn new(bus: &'a Mutex<M, RefCell<BUS>>) -> Self {
BUS: i2c::Error + Debug,
{
fn kind(&self) -> i2c::ErrorKind {
match self {
Self::I2c(e) => e.kind(),
}
}
}
pub struct I2cBusDevice<'a, BUS> {
bus: &'a RefCell<BUS>,
}
impl<'a, BUS> I2cBusDevice<'a, BUS> {
pub fn new(bus: &'a RefCell<BUS>) -> Self {
Self { bus } Self { bus }
} }
} }
impl<'a, BUS> i2c::ErrorType for I2cBusDevice<'a, BUS> impl<'a, M: RawMutex, BUS> ErrorType for I2cBusDevice<'a, M, BUS>
where where
BUS: i2c::ErrorType, BUS: ErrorType,
{ {
type Error = I2cBusDeviceError<BUS::Error>; type Error = I2cBusDeviceError<BUS::Error>;
} }
impl<M, BUS> i2c::I2c for I2cBusDevice<'_, BUS> impl<M, BUS> I2c for I2cBusDevice<'_, M, BUS>
where where
BUS: i2c::I2c, M: RawMutex,
BUS: I2c,
{ {
fn read(&mut self, address: u8, buffer: &mut [u8]) -> Result<(), Self::Error> { fn read(&mut self, address: u8, buffer: &mut [u8]) -> Result<(), Self::Error> {
let mut bus = self.bus.borrow_mut(); self.bus
bus.read(address, buffer).map_err(I2cBusDeviceError::I2c)?; .lock(|bus| bus.borrow_mut().read(address, buffer).map_err(I2cBusDeviceError::I2c))
Ok(())
} }
fn write(&mut self, address: u8, bytes: &[u8]) -> Result<(), Self::Error> { fn write(&mut self, address: u8, bytes: &[u8]) -> Result<(), Self::Error> {
let mut bus = self.bus.borrow_mut(); self.bus
bus.write(address, bytes).map_err(I2cBusDeviceError::I2c)?; .lock(|bus| bus.borrow_mut().write(address, bytes).map_err(I2cBusDeviceError::I2c))
Ok(())
} }
fn write_read(&mut self, address: u8, wr_buffer: &[u8], rd_buffer: &mut [u8]) -> Result<(), Self::Error> { fn write_read(&mut self, address: u8, wr_buffer: &[u8], rd_buffer: &mut [u8]) -> Result<(), Self::Error> {
let mut bus = self.bus.borrow_mut(); self.bus.lock(|bus| {
bus.write_read(address, wr_buffer, rd_buffer) bus.borrow_mut()
.map_err(I2cBusDeviceError::I2c)?; .write_read(address, wr_buffer, rd_buffer)
Ok(()) .map_err(I2cBusDeviceError::I2c)
})
} }
fn transaction<'a>(&mut self, address: u8, operations: &mut [i2c::Operation<'a>]) -> Result<(), Self::Error> { fn transaction<'a>(&mut self, address: u8, operations: &mut [Operation<'a>]) -> Result<(), Self::Error> {
let _ = address;
let _ = operations;
todo!()
}
fn write_iter<B: IntoIterator<Item = u8>>(&mut self, addr: u8, bytes: B) -> Result<(), Self::Error> {
let _ = addr;
let _ = bytes;
todo!()
}
fn write_iter_read<B: IntoIterator<Item = u8>>(
&mut self,
addr: u8,
bytes: B,
buffer: &mut [u8],
) -> Result<(), Self::Error> {
let _ = addr;
let _ = bytes;
let _ = buffer;
todo!()
}
fn transaction_iter<'a, O: IntoIterator<Item = Operation<'a>>>(
&mut self,
address: u8,
operations: O,
) -> Result<(), Self::Error> {
let _ = address; let _ = address;
let _ = operations; let _ = operations;
todo!() todo!()

View file

@ -4,7 +4,7 @@ use core::fmt::Debug;
use embedded_hal_1::digital::blocking::OutputPin; use embedded_hal_1::digital::blocking::OutputPin;
use embedded_hal_1::spi; use embedded_hal_1::spi;
use embedded_hal_1::spi::blocking::SpiDevice; use embedded_hal_1::spi::blocking::{SpiBusFlush, SpiDevice};
#[derive(Copy, Clone, Eq, PartialEq, Debug)] #[derive(Copy, Clone, Eq, PartialEq, Debug)]
pub enum SpiBusDeviceError<BUS, CS> { pub enum SpiBusDeviceError<BUS, CS> {
@ -44,15 +44,15 @@ where
type Error = SpiBusDeviceError<BUS::Error, CS::Error>; type Error = SpiBusDeviceError<BUS::Error, CS::Error>;
} }
impl<BUS, CS> spi::SpiDevice for SpiBusDevice<'_, BUS, CS> impl<BUS, CS> SpiDevice for SpiBusDevice<'_, BUS, CS>
where where
BUS: spi::SpiBusFlush, BUS: SpiBusFlush,
CS: OutputPin, CS: OutputPin,
{ {
type Bus = BUS; type Bus = BUS;
fn transaction<R>(&mut self, f: impl FnOnce(&mut Self::Bus) -> Result<R, BUS::Error>) -> Result<R, Self::Error> { fn transaction<R>(&mut self, f: impl FnOnce(&mut Self::Bus) -> Result<R, BUS::Error>) -> Result<R, Self::Error> {
let mut bus = self.bus.borrow_mut(); let mut bus = self.bus.borrow_mut();
self.cs.set_low().map_err(SpiDeviceWithCsError::Cs)?; self.cs.set_low().map_err(SpiBusDeviceError::Cs)?;
let f_res = f(&mut bus); let f_res = f(&mut bus);
@ -60,9 +60,9 @@ where
let flush_res = bus.flush(); let flush_res = bus.flush();
let cs_res = self.cs.set_high(); let cs_res = self.cs.set_high();
let f_res = f_res.map_err(SpiDeviceWithCsError::Spi)?; let f_res = f_res.map_err(SpiBusDeviceError::Spi)?;
flush_res.map_err(SpiDeviceWithCsError::Spi)?; flush_res.map_err(SpiBusDeviceError::Spi)?;
cs_res.map_err(SpiDeviceWithCsError::Cs)?; cs_res.map_err(SpiBusDeviceError::Cs)?;
Ok(f_res) Ok(f_res)
} }