update metapac after stm32-data PR323

and refactor a few code with cargo clippy

embassy-stm32/Cargo.toml

@@ -57,7 +57,7 @@ futures = { version = "0.3.17", default-features = false, features = ["async-awa
 rand_core = "0.6.3"
 sdio-host = "0.5.0"
 critical-section = "1.1"
-stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-2234f380f51d16d0398b8e547088b33ea623cc7c" }
+stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-8caf2f0bda28baf4393899dc67ba57f058087f5a" }
 vcell = "0.1.3"
 bxcan = "0.7.0"
 nb = "1.0.0"
@@ -75,7 +75,7 @@ critical-section = { version = "1.1", features = ["std"] }
 [build-dependencies]
 proc-macro2 = "1.0.36"
 quote = "1.0.15"
-stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-2234f380f51d16d0398b8e547088b33ea623cc7c", default-features = false, features = ["metadata"]}
+stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-8caf2f0bda28baf4393899dc67ba57f058087f5a", default-features = false, features = ["metadata"]}
 
 
 [features]

embassy-stm32/src/can/bxcan.rs

@@ -1,3 +1,4 @@
+use core::convert::AsMut;
 use core::future::poll_fn;
 use core::marker::PhantomData;
 use core::ops::{Deref, DerefMut};
@@ -10,7 +11,7 @@ use futures::FutureExt;
 
 use crate::gpio::sealed::AFType;
 use crate::interrupt::typelevel::Interrupt;
-use crate::pac::can::vals::{Lec, RirIde};
+use crate::pac::can::vals::{Ide, Lec};
 use crate::rcc::RccPeripheral;
 use crate::time::Hertz;
 use crate::{interrupt, peripherals, Peripheral};
@@ -148,15 +149,11 @@ impl<'d, T: Instance> Can<'d, T> {
         T::enable_and_reset();
 
         {
-            use crate::pac::can::vals::{Errie, Fmpie, Tmeie};
-
             T::regs().ier().write(|w| {
-                // TODO: fix metapac
+                w.set_errie(true);
-
+                w.set_fmpie(0, true);
-                w.set_errie(Errie::from_bits(1));
+                w.set_fmpie(1, true);
-                w.set_fmpie(0, Fmpie::from_bits(1));
+                w.set_tmeie(true);
-                w.set_fmpie(1, Fmpie::from_bits(1));
-                w.set_tmeie(Tmeie::from_bits(1));
             });
 
             T::regs().mcr().write(|w| {
@@ -276,7 +273,7 @@ impl<'d, T: Instance> Can<'d, T> {
             }
 
             let rir = fifo.rir().read();
-            let id = if rir.ide() == RirIde::STANDARD {
+            let id = if rir.ide() == Ide::STANDARD {
                 Id::from(StandardId::new_unchecked(rir.stid()))
             } else {
                 let stid = (rir.stid() & 0x7FF) as u32;
@@ -403,9 +400,11 @@ impl<'d, T: Instance> Can<'d, T> {
         let (tx, rx0, rx1) = self.can.split_by_ref();
         (CanTx { tx }, CanRx { rx0, rx1 })
     }
+}
 
+impl<'d, T: Instance> AsMut<bxcan::Can<BxcanInstance<'d, T>>> for Can<'d, T> {
     /// Get mutable access to the lower-level driver from the `bxcan` crate.
-    pub fn as_mut(&mut self) -> &mut bxcan::Can<BxcanInstance<'d, T>> {
+    fn as_mut(&mut self) -> &mut bxcan::Can<BxcanInstance<'d, T>> {
         &mut self.can
     }
 }

embassy-stm32/src/rtc/v2.rs

@@ -1,4 +1,4 @@
-use stm32_metapac::rtc::vals::{Init, Osel, Pol};
+use stm32_metapac::rtc::vals::{Osel, Pol};
 
 use super::sealed;
 use crate::pac::rtc::Rtc;
@@ -49,7 +49,7 @@ impl super::Rtc {
             clock_drift = RTC_CALR_MAX_PPM;
         }
 
-        clock_drift = clock_drift / RTC_CALR_RESOLUTION_PPM;
+        clock_drift /= RTC_CALR_RESOLUTION_PPM;
 
         self.write(false, |rtc| {
             rtc.calr().write(|w| {
@@ -107,7 +107,7 @@ impl super::Rtc {
         // true if initf bit indicates RTC peripheral is in init mode
         if init_mode && !r.isr().read().initf() {
             // to update calendar date/time, time format, and prescaler configuration, RTC must be in init mode
-            r.isr().modify(|w| w.set_init(Init::INITMODE));
+            r.isr().modify(|w| w.set_init(true));
             // wait till init state entered
             // ~2 RTCCLK cycles
             while !r.isr().read().initf() {}
@@ -116,7 +116,7 @@ impl super::Rtc {
         let result = f(&r);
 
         if init_mode {
-            r.isr().modify(|w| w.set_init(Init::FREERUNNINGMODE)); // Exits init mode
+            r.isr().modify(|w| w.set_init(false)); // Exits init mode
         }
 
         // Re-enable write protection.

embassy-stm32/src/rtc/v3.rs

@@ -1,4 +1,4 @@
-use stm32_metapac::rtc::vals::{Calp, Calw16, Calw8, Fmt, Init, Key, Osel, Pol, TampalrmPu, TampalrmType};
+use stm32_metapac::rtc::vals::{Calp, Calw16, Calw8, Fmt, Key, Osel, Pol, TampalrmType};
 
 use super::{sealed, RtcCalibrationCyclePeriod};
 use crate::pac::rtc::Rtc;
@@ -26,7 +26,7 @@ impl super::Rtc {
             rtc.cr().modify(|w| {
                 w.set_out2en(false);
                 w.set_tampalrm_type(TampalrmType::PUSHPULL);
-                w.set_tampalrm_pu(TampalrmPu::NOPULLUP);
+                w.set_tampalrm_pu(false);
             });
         });
     }
@@ -106,7 +106,7 @@ impl super::Rtc {
         r.wpr().write(|w| w.set_key(Key::DEACTIVATE2));
 
         if init_mode && !r.icsr().read().initf() {
-            r.icsr().modify(|w| w.set_init(Init::INITMODE));
+            r.icsr().modify(|w| w.set_init(true));
             // wait till init state entered
             // ~2 RTCCLK cycles
             while !r.icsr().read().initf() {}
@@ -115,7 +115,7 @@ impl super::Rtc {
         let result = f(&r);
 
         if init_mode {
-            r.icsr().modify(|w| w.set_init(Init::FREERUNNINGMODE)); // Exits init mode
+            r.icsr().modify(|w| w.set_init(false)); // Exits init mode
         }
 
         // Re-enable write protection.

embassy-stm32/src/spi/mod.rs

@@ -311,7 +311,7 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
                 w.set_ssom(vals::Ssom::ASSERTED);
                 w.set_midi(0);
                 w.set_mssi(0);
-                w.set_afcntr(vals::Afcntr::CONTROLLED);
+                w.set_afcntr(true);
                 w.set_ssiop(vals::Ssiop::ACTIVEHIGH);
             });
             T::REGS.cfg1().modify(|w| {

examples/stm32f4/src/bin/ws2812_pwm_dma.rs

@@ -21,7 +21,6 @@
 use embassy_executor::Spawner;
 use embassy_stm32::gpio::OutputType;
 use embassy_stm32::pac;
-use embassy_stm32::pac::timer::vals::Ocpe;
 use embassy_stm32::time::khz;
 use embassy_stm32::timer::simple_pwm::{PwmPin, SimplePwm};
 use embassy_stm32::timer::{Channel, CountingMode};
@@ -94,7 +93,7 @@ async fn main(_spawner: Spawner) {
     // keep output waveform integrity
     pac::TIM3
         .ccmr_output(pwm_channel.index())
-        .modify(|v| v.set_ocpe(0, Ocpe::ENABLED));
+        .modify(|v| v.set_ocpe(0, true));
 
     // make sure PWM output keep low on first start
     ws2812_pwm.set_duty(pwm_channel, 0);

examples/stm32h7/src/bin/dac_dma.rs

@@ -4,7 +4,7 @@
 use defmt::*;
 use embassy_executor::Spawner;
 use embassy_stm32::dac::{DacCh1, DacCh2, ValueArray};
-use embassy_stm32::pac::timer::vals::{Mms, Opm};
+use embassy_stm32::pac::timer::vals::Mms;
 use embassy_stm32::peripherals::{DAC1, DMA1_CH3, DMA1_CH4, TIM6, TIM7};
 use embassy_stm32::rcc::low_level::RccPeripheral;
 use embassy_stm32::time::Hertz;
@@ -78,7 +78,7 @@ async fn dac_task1(mut dac: DacCh1<'static, DAC1, DMA1_CH3>) {
     TIM6::regs().arr().modify(|w| w.set_arr(reload as u16 - 1));
     TIM6::regs().cr2().modify(|w| w.set_mms(Mms::UPDATE));
     TIM6::regs().cr1().modify(|w| {
-        w.set_opm(Opm::DISABLED);
+        w.set_opm(false);
         w.set_cen(true);
     });
 
@@ -115,7 +115,7 @@ async fn dac_task2(mut dac: DacCh2<'static, DAC1, DMA1_CH4>) {
     TIM7::regs().arr().modify(|w| w.set_arr(reload as u16 - 1));
     TIM7::regs().cr2().modify(|w| w.set_mms(Mms::UPDATE));
     TIM7::regs().cr1().modify(|w| {
-        w.set_opm(Opm::DISABLED);
+        w.set_opm(false);
         w.set_cen(true);
     });
 

examples/stm32l4/src/bin/dac_dma.rs

@@ -4,7 +4,7 @@
 use defmt::*;
 use embassy_executor::Spawner;
 use embassy_stm32::dac::{DacCh1, DacCh2, ValueArray};
-use embassy_stm32::pac::timer::vals::{Mms, Opm};
+use embassy_stm32::pac::timer::vals::Mms;
 use embassy_stm32::peripherals::{DAC1, DMA1_CH3, DMA1_CH4, TIM6, TIM7};
 use embassy_stm32::rcc::low_level::RccPeripheral;
 use embassy_stm32::time::Hertz;
@@ -49,7 +49,7 @@ async fn dac_task1(mut dac: DacCh1<'static, DAC1, DMA1_CH3>) {
     TIM6::regs().arr().modify(|w| w.set_arr(reload as u16 - 1));
     TIM6::regs().cr2().modify(|w| w.set_mms(Mms::UPDATE));
     TIM6::regs().cr1().modify(|w| {
-        w.set_opm(Opm::DISABLED);
+        w.set_opm(false);
         w.set_cen(true);
     });
 
@@ -86,7 +86,7 @@ async fn dac_task2(mut dac: DacCh2<'static, DAC1, DMA1_CH4>) {
     TIM7::regs().arr().modify(|w| w.set_arr(reload as u16 - 1));
     TIM7::regs().cr2().modify(|w| w.set_mms(Mms::UPDATE));
     TIM7::regs().cr1().modify(|w| {
-        w.set_opm(Opm::DISABLED);
+        w.set_opm(false);
         w.set_cen(true);
     });