cyw43-pio: add overclock feature flag.
This commit is contained in:
Dario Nieuwenhuis
parent
8800caa216
commit
db907a914c
4 changed files with 60 additions and 31 deletions
5
ci.sh
5
ci.sh
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@ -1,7 +1,9 @@
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#!/bin/bash
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set -euxo pipefail
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cd $(dirname $0)
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export CARGO_TARGET_DIR=$(pwd)/target
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export DEFMT_LOG=trace
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# build examples
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@ -18,3 +20,6 @@ cargo build --target thumbv6m-none-eabi --features 'log'
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cargo build --target thumbv6m-none-eabi --features 'defmt'
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cargo build --target thumbv6m-none-eabi --features 'log,firmware-logs'
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cargo build --target thumbv6m-none-eabi --features 'defmt,firmware-logs'
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(cd cyw43-pio; cargo build --target thumbv6m-none-eabi --features '')
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(cd cyw43-pio; cargo build --target thumbv6m-none-eabi --features 'overclock')
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@ -3,6 +3,11 @@ name = "cyw43-pio"
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version = "0.1.0"
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edition = "2021"
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[features]
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# If disabled, SPI runs at 31.25MHz
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# If enabled, SPI runs at 62.5MHz, which is 25% higher than 50Mhz which is the maximum according to the CYW43439 datasheet.
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overclock = []
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[dependencies]
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cyw43 = { path = "../" }
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embassy-rp = { version = "0.1.0", features = ["unstable-traits", "nightly", "unstable-pac", "time-driver"] }
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@ -40,24 +40,46 @@ where
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DIO: PioPin,
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CLK: PioPin,
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{
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#[cfg(feature = "overclock")]
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let program = pio_asm!(
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".side_set 1"
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".wrap_target"
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// write out x-1 bits
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"lp:",
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"lp:"
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"out pins, 1 side 0"
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"jmp x-- lp side 1"
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// switch directions
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"set pindirs, 0 side 0"
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// these nops seem to be necessary for fast clkdiv
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//"nop side 1"
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//"nop side 0"
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"nop side 1"
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"nop side 1" // necessary for clkdiv=1.
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"nop side 0"
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// read in y-1 bits
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"lp2:"
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"in pins, 1 side 0"
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"jmp y-- lp2 side 1"
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"in pins, 1 side 1"
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"jmp y-- lp2 side 0"
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// wait for event and irq host
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"wait 1 pin 0 side 0"
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"irq 0 side 0"
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".wrap"
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);
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#[cfg(not(feature = "overclock"))]
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let program = pio_asm!(
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".side_set 1"
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".wrap_target"
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// write out x-1 bits
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"lp:"
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"out pins, 1 side 0"
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"jmp x-- lp side 1"
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// switch directions
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"set pindirs, 0 side 0"
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"nop side 0"
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// read in y-1 bits
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"lp2:"
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"in pins, 1 side 1"
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"jmp y-- lp2 side 0"
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// wait for event and irq host
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"wait 1 pin 0 side 0"
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@ -72,8 +94,8 @@ where
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pin_io.set_pull(Pull::None);
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pin_io.set_schmitt(true);
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pin_io.set_input_sync_bypass(true);
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//pin_io.set_drive_strength(Drive::_12mA);
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//pin_io.set_slew_rate(SlewRate::Fast);
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pin_io.set_drive_strength(Drive::_12mA);
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pin_io.set_slew_rate(SlewRate::Fast);
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let mut pin_clk = common.make_pio_pin(clk);
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pin_clk.set_drive_strength(Drive::_12mA);
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@ -91,27 +113,24 @@ where
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cfg.shift_in.auto_fill = true;
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//cfg.shift_in.threshold = 32;
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// theoretical maximum according to data sheet, 100Mhz Pio => 50Mhz SPI Freq
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// seems to cause random corruption, probably due to jitter due to the fractional divider.
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// cfg.clock_divider = FixedU32::from_bits(0x0140);
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#[cfg(feature = "overclock")]
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{
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// 125mhz Pio => 62.5Mhz SPI Freq. 25% higher than theoretical maximum according to
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// data sheet, but seems to work fine.
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cfg.clock_divider = FixedU32::from_bits(0x0100);
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}
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#[cfg(not(feature = "overclock"))]
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{
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// same speed as pico-sdk, 62.5Mhz
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// This is actually the fastest we can go without overclocking.
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// According to data sheet, the theoretical maximum is 100Mhz Pio => 50Mhz SPI Freq.
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// However, the PIO uses a fractional divider, which works by introducing jitter when
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// the divider is not an integer. It does some clocks at 125mhz and others at 62.5mhz
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// so that it averages out to the desired frequency of 100mhz. The 125mhz clock cycles
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// violate the maximum from the data sheet.
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cfg.clock_divider = FixedU32::from_bits(0x0200);
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// 32 Mhz
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// cfg.clock_divider = FixedU32::from_bits(0x03E8);
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// 16 Mhz
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// cfg.clock_divider = FixedU32::from_bits(0x07d0);
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// 8Mhz
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// cfg.clock_divider = FixedU32::from_bits(0x0a_00);
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// 1Mhz
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// cfg.clock_divider = FixedU32::from_bits(0x7d_00);
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// slowest possible
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// cfg.clock_divider = FixedU32::from_bits(0xffff_00);
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}
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sm.set_config(&cfg);
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@ -6,7 +6,7 @@ edition = "2021"
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[dependencies]
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cyw43 = { path = "../../", features = ["defmt", "firmware-logs"] }
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cyw43-pio = { path = "../../cyw43-pio", features = ["defmt"] }
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cyw43-pio = { path = "../../cyw43-pio", features = ["defmt", "overclock"] }
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embassy-executor = { version = "0.2.0", features = ["defmt", "integrated-timers", "executor-thread", "arch-cortex-m"] }
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embassy-time = { version = "0.1.0", features = ["defmt", "defmt-timestamp-uptime"] }
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embassy-rp = { version = "0.1.0", features = ["defmt", "unstable-traits", "nightly", "unstable-pac", "time-driver"] }
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@ -48,7 +48,7 @@ debug = 1
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debug-assertions = false
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incremental = false
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lto = 'fat'
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opt-level = 'z'
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opt-level = 's'
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overflow-checks = false
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# do not optimize proc-macro crates = faster builds from scratch
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