Review comments. Corrected unused fields.
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4f2f375777
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1 changed files with 19 additions and 19 deletions
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@ -148,14 +148,14 @@ impl Iterator for BitIter {
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/// GPIOTE channel driver in input mode
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pub struct InputChannel<'d, C: Channel, T: GpioPin> {
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_ch: PeripheralRef<'d, C>,
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_pin: Input<'d, T>,
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ch: PeripheralRef<'d, C>,
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pin: Input<'d, T>,
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}
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impl<'d, C: Channel, T: GpioPin> Drop for InputChannel<'d, C, T> {
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fn drop(&mut self) {
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let g = regs();
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let num = self._ch.number();
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let num = self.ch.number();
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g.config[num].write(|w| w.mode().disabled());
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g.intenclr.write(|w| unsafe { w.bits(1 << num) });
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}
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@ -185,12 +185,12 @@ impl<'d, C: Channel, T: GpioPin> InputChannel<'d, C, T> {
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g.events_in[num].reset();
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InputChannel { _ch: ch, _pin: pin }
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InputChannel { ch, pin }
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}
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pub async fn wait(&self) {
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let g = regs();
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let num = self._ch.number();
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let num = self.ch.number();
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// Enable interrupt
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g.events_in[num].reset();
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@ -211,20 +211,20 @@ impl<'d, C: Channel, T: GpioPin> InputChannel<'d, C, T> {
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/// Returns the IN event, for use with PPI.
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pub fn event_in(&self) -> Event {
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let g = regs();
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Event::from_reg(&g.events_in[self._ch.number()])
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Event::from_reg(&g.events_in[self.ch.number()])
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}
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}
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/// GPIOTE channel driver in output mode
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pub struct OutputChannel<'d, C: Channel, T: GpioPin> {
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_ch: PeripheralRef<'d, C>,
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ch: PeripheralRef<'d, C>,
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_pin: Output<'d, T>,
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}
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impl<'d, C: Channel, T: GpioPin> Drop for OutputChannel<'d, C, T> {
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fn drop(&mut self) {
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let g = regs();
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let num = self._ch.number();
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let num = self.ch.number();
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g.config[num].write(|w| w.mode().disabled());
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g.intenclr.write(|w| unsafe { w.bits(1 << num) });
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}
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@ -255,47 +255,47 @@ impl<'d, C: Channel, T: GpioPin> OutputChannel<'d, C, T> {
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unsafe { w.psel().bits(pin.pin.pin.pin()) }
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});
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OutputChannel { _ch: ch, _pin: pin }
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OutputChannel { ch, _pin: pin }
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}
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/// Triggers `task out` (as configured with task_out_polarity, defaults to Toggle).
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pub fn out(&self) {
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let g = regs();
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g.tasks_out[self._ch.number()].write(|w| unsafe { w.bits(1) });
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g.tasks_out[self.ch.number()].write(|w| unsafe { w.bits(1) });
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}
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/// Triggers `task set` (set associated pin high).
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#[cfg(not(feature = "nrf51"))]
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pub fn set(&self) {
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let g = regs();
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g.tasks_set[self._ch.number()].write(|w| unsafe { w.bits(1) });
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g.tasks_set[self.ch.number()].write(|w| unsafe { w.bits(1) });
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}
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/// Triggers `task clear` (set associated pin low).
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#[cfg(not(feature = "nrf51"))]
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pub fn clear(&self) {
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let g = regs();
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g.tasks_clr[self._ch.number()].write(|w| unsafe { w.bits(1) });
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g.tasks_clr[self.ch.number()].write(|w| unsafe { w.bits(1) });
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}
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/// Returns the OUT task, for use with PPI.
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pub fn task_out(&self) -> Task {
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let g = regs();
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Task::from_reg(&g.tasks_out[self._ch.number()])
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Task::from_reg(&g.tasks_out[self.ch.number()])
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}
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/// Returns the CLR task, for use with PPI.
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#[cfg(not(feature = "nrf51"))]
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pub fn task_clr(&self) -> Task {
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let g = regs();
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Task::from_reg(&g.tasks_clr[self._ch.number()])
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Task::from_reg(&g.tasks_clr[self.ch.number()])
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}
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/// Returns the SET task, for use with PPI.
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#[cfg(not(feature = "nrf51"))]
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pub fn task_set(&self) -> Task {
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let g = regs();
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Task::from_reg(&g.tasks_set[self._ch.number()])
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Task::from_reg(&g.tasks_set[self.ch.number()])
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}
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}
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@ -443,11 +443,11 @@ mod eh02 {
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type Error = Infallible;
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fn is_high(&self) -> Result<bool, Self::Error> {
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Ok(self._pin.is_high())
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Ok(self.pin.is_high())
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}
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fn is_low(&self) -> Result<bool, Self::Error> {
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Ok(self._pin.is_low())
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Ok(self.pin.is_low())
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}
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}
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}
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@ -462,11 +462,11 @@ mod eh1 {
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impl<'d, C: Channel, T: GpioPin> embedded_hal_1::digital::InputPin for InputChannel<'d, C, T> {
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fn is_high(&self) -> Result<bool, Self::Error> {
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Ok(self._pin.is_high())
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Ok(self.pin.is_high())
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}
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fn is_low(&self) -> Result<bool, Self::Error> {
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Ok(self._pin.is_low())
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Ok(self.pin.is_low())
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}
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}
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}
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