Merge pull request #66 from mattiasgronlund/remove_myspi
Remove MySpi from example
This commit is contained in:
commit
efb67dfc1b
1 changed files with 2 additions and 93 deletions
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@ -4,7 +4,6 @@
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#![feature(async_fn_in_trait)]
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#![feature(async_fn_in_trait)]
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#![allow(incomplete_features)]
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#![allow(incomplete_features)]
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use core::slice;
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use core::str::from_utf8;
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use core::str::from_utf8;
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use cyw43_pio::PioSpi;
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use cyw43_pio::PioSpi;
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@ -12,8 +11,8 @@ use defmt::*;
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use embassy_executor::Spawner;
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use embassy_executor::Spawner;
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use embassy_net::tcp::TcpSocket;
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use embassy_net::tcp::TcpSocket;
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use embassy_net::{Config, Stack, StackResources};
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use embassy_net::{Config, Stack, StackResources};
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use embassy_rp::gpio::{Flex, Level, Output};
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use embassy_rp::gpio::{Level, Output};
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use embassy_rp::peripherals::{DMA_CH0, PIN_23, PIN_24, PIN_25, PIN_29};
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use embassy_rp::peripherals::{DMA_CH0, PIN_23, PIN_25};
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use embassy_rp::pio::{Pio0, PioPeripheral, PioStateMachineInstance, Sm0};
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use embassy_rp::pio::{Pio0, PioPeripheral, PioStateMachineInstance, Sm0};
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use embedded_io::asynch::Write;
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use embedded_io::asynch::Write;
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use static_cell::StaticCell;
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use static_cell::StaticCell;
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@ -62,11 +61,6 @@ async fn main(spawner: Spawner) {
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let pwr = Output::new(p.PIN_23, Level::Low);
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let pwr = Output::new(p.PIN_23, Level::Low);
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let cs = Output::new(p.PIN_25, Level::High);
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let cs = Output::new(p.PIN_25, Level::High);
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// let clk = Output::new(p.PIN_29, Level::Low);
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// let mut dio = Flex::new(p.PIN_24);
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// dio.set_low();
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// dio.set_as_output();
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// // let bus = MySpi { clk, dio };
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let (_, sm, _, _, _) = p.PIO0.split();
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let (_, sm, _, _, _) = p.PIO0.split();
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let dma = p.DMA_CH0;
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let dma = p.DMA_CH0;
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@ -150,88 +144,3 @@ async fn main(spawner: Spawner) {
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}
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}
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}
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}
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struct MySpi {
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/// SPI clock
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clk: Output<'static, PIN_29>,
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/// 4 signals, all in one!!
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/// - SPI MISO
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/// - SPI MOSI
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/// - IRQ
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/// - strap to set to gSPI mode on boot.
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dio: Flex<'static, PIN_24>,
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/// Chip select
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cs: Output<'static, PIN_25>,
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}
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impl MySpi {
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async fn read(&mut self, words: &mut [u32]) {
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self.dio.set_as_input();
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for word in words {
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let mut w = 0;
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for _ in 0..32 {
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w = w << 1;
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// rising edge, sample data
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if self.dio.is_high() {
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w |= 0x01;
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}
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self.clk.set_high();
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// falling edge
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self.clk.set_low();
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}
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*word = w
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}
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}
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async fn write(&mut self, words: &[u32]) {
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self.dio.set_as_output();
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for word in words {
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let mut word = *word;
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for _ in 0..32 {
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// falling edge, setup data
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self.clk.set_low();
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if word & 0x8000_0000 == 0 {
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self.dio.set_low();
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} else {
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self.dio.set_high();
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}
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// rising edge
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self.clk.set_high();
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word = word << 1;
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}
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}
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self.clk.set_low();
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self.dio.set_as_input();
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}
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}
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impl cyw43::SpiBusCyw43 for MySpi {
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async fn cmd_write(&mut self, write: &[u32]) -> u32 {
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self.cs.set_low();
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self.write(write).await;
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let mut status = 0;
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self.read(slice::from_mut(&mut status)).await;
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self.cs.set_high();
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status
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}
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async fn cmd_read(&mut self, write: u32, read: &mut [u32]) -> u32 {
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self.cs.set_low();
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self.write(slice::from_ref(&write)).await;
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self.read(read).await;
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let mut status = 0;
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self.read(slice::from_mut(&mut status)).await;
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self.cs.set_high();
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status
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}
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}
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