Merge #481
481: Stm32u5 r=Dirbaio a=bobmcwhirter Co-authored-by: Bob McWhirter <bmcwhirt@redhat.com>
This commit is contained in:
bors[bot]
GitHub
commit
fc75e0ec57
5 changed files with 544 additions and 7 deletions
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@ -1 +1,32 @@
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use crate::peripherals;
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/// Voltage Scale
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///
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/// Represents the voltage range feeding the CPU core. The maximum core
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/// clock frequency depends on this value.
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#[derive(Copy, Clone, PartialEq)]
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pub enum VoltageScale {
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// Highest frequency
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Range1,
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Range2,
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Range3,
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// Lowest power
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Range4,
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}
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/// Power Configuration
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///
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/// Generated when the PWR peripheral is frozen. The existence of this
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/// value indicates that the voltage scaling configuration can no
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/// longer be changed.
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pub struct Power {
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pub(crate) vos: VoltageScale,
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}
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impl Power {
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pub fn new(_peri: peripherals::PWR) -> Self {
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Self {
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vos: VoltageScale::Range4,
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}
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}
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}
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@ -1,8 +1,295 @@
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pub struct Config {}
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use crate::pac;
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use crate::peripherals::{self, RCC};
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use crate::pwr::{Power, VoltageScale};
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use crate::rcc::{set_freqs, Clocks};
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use crate::time::{Hertz, U32Ext};
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use stm32_metapac::rcc::vals::{Hpre, Msirange, Msirgsel, Pllm, Pllsrc, Ppre, Sw};
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/// HSI16 speed
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pub const HSI16_FREQ: u32 = 16_000_000;
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#[derive(Copy, Clone)]
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pub enum ClockSrc {
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MSI(MSIRange),
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HSE(Hertz),
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HSI16,
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PLL1R(PllSrc, PllM, PllN, PllClkDiv),
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}
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#[derive(Clone, Copy, Debug)]
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pub enum PllSrc {
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MSI(MSIRange),
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HSE(Hertz),
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HSI16,
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}
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impl Into<Pllsrc> for PllSrc {
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fn into(self) -> Pllsrc {
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match self {
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PllSrc::MSI(..) => Pllsrc::MSIS,
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PllSrc::HSE(..) => Pllsrc::HSE,
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PllSrc::HSI16 => Pllsrc::HSI16,
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}
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}
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}
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seq_macro::seq!(N in 2..=128 {
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#[derive(Copy, Clone, Debug)]
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pub enum PllClkDiv {
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NotDivided,
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#(
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Div#N = (N-1),
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)*
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}
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impl PllClkDiv {
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fn to_div(&self) -> u8 {
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match self {
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PllClkDiv::NotDivided => 1,
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#(
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PllClkDiv::Div#N => (N + 1),
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)*
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}
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}
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}
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});
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impl Into<u8> for PllClkDiv {
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fn into(self) -> u8 {
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(self as u8) + 1
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}
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}
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seq_macro::seq!(N in 4..=512 {
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#[derive(Copy, Clone, Debug)]
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pub enum PllN {
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NotMultiplied,
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#(
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Mul#N = (N-1),
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)*
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}
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impl PllN {
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fn to_mul(&self) -> u16 {
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match self {
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PllN::NotMultiplied => 1,
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#(
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PllN::Mul#N => (N + 1),
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)*
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}
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}
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}
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});
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impl Into<u16> for PllN {
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fn into(self) -> u16 {
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(self as u16) + 1
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}
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}
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// Pre-division
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#[derive(Copy, Clone, Debug)]
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pub enum PllM {
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NotDivided = 0b0000,
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Div2 = 0b0001,
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Div3 = 0b0010,
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Div4 = 0b0011,
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Div5 = 0b0100,
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Div6 = 0b0101,
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Div7 = 0b0110,
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Div8 = 0b0111,
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Div9 = 0b1000,
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Div10 = 0b1001,
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Div11 = 0b1010,
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Div12 = 0b1011,
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Div13 = 0b1100,
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Div14 = 0b1101,
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Div15 = 0b1110,
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Div16 = 0b1111,
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}
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impl Into<Pllm> for PllM {
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fn into(self) -> Pllm {
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Pllm(self as u8)
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}
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}
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/// AHB prescaler
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#[derive(Clone, Copy, PartialEq)]
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pub enum AHBPrescaler {
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NotDivided,
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Div2,
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Div4,
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Div8,
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Div16,
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Div64,
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Div128,
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Div256,
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Div512,
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}
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impl Into<Hpre> for AHBPrescaler {
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fn into(self) -> Hpre {
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match self {
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AHBPrescaler::NotDivided => Hpre::NONE,
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AHBPrescaler::Div2 => Hpre::DIV2,
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AHBPrescaler::Div4 => Hpre::DIV4,
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AHBPrescaler::Div8 => Hpre::DIV8,
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AHBPrescaler::Div16 => Hpre::DIV16,
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AHBPrescaler::Div64 => Hpre::DIV64,
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AHBPrescaler::Div128 => Hpre::DIV128,
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AHBPrescaler::Div256 => Hpre::DIV256,
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AHBPrescaler::Div512 => Hpre::DIV512,
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}
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}
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}
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impl Into<u8> for AHBPrescaler {
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fn into(self) -> u8 {
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match self {
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AHBPrescaler::NotDivided => 1,
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AHBPrescaler::Div2 => 0x08,
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AHBPrescaler::Div4 => 0x09,
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AHBPrescaler::Div8 => 0x0a,
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AHBPrescaler::Div16 => 0x0b,
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AHBPrescaler::Div64 => 0x0c,
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AHBPrescaler::Div128 => 0x0d,
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AHBPrescaler::Div256 => 0x0e,
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AHBPrescaler::Div512 => 0x0f,
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}
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}
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}
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impl Default for AHBPrescaler {
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fn default() -> Self {
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AHBPrescaler::NotDivided
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}
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}
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/// APB prescaler
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#[derive(Clone, Copy)]
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pub enum APBPrescaler {
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NotDivided,
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Div2,
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Div4,
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Div8,
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Div16,
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}
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impl Into<Ppre> for APBPrescaler {
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fn into(self) -> Ppre {
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match self {
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APBPrescaler::NotDivided => Ppre::NONE,
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APBPrescaler::Div2 => Ppre::DIV2,
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APBPrescaler::Div4 => Ppre::DIV4,
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APBPrescaler::Div8 => Ppre::DIV8,
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APBPrescaler::Div16 => Ppre::DIV16,
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}
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}
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}
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impl Default for APBPrescaler {
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fn default() -> Self {
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APBPrescaler::NotDivided
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}
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}
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impl Into<u8> for APBPrescaler {
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fn into(self) -> u8 {
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match self {
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APBPrescaler::NotDivided => 1,
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APBPrescaler::Div2 => 0x04,
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APBPrescaler::Div4 => 0x05,
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APBPrescaler::Div8 => 0x06,
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APBPrescaler::Div16 => 0x07,
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}
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}
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}
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impl Into<Sw> for ClockSrc {
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fn into(self) -> Sw {
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match self {
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ClockSrc::MSI(..) => Sw::MSIS,
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ClockSrc::HSE(..) => Sw::HSE,
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ClockSrc::HSI16 => Sw::HSI16,
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ClockSrc::PLL1R(..) => Sw::PLL1R,
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}
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}
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}
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#[derive(Debug, Copy, Clone)]
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pub enum MSIRange {
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Range48mhz = 48_000_000,
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Range24mhz = 24_000_000,
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Range16mhz = 16_000_000,
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Range12mhz = 12_000_000,
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Range4mhz = 4_000_000,
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Range2mhz = 2_000_000,
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Range1_33mhz = 1_330_000,
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Range1mhz = 1_000_000,
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Range3_072mhz = 3_072_000,
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Range1_536mhz = 1_536_000,
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Range1_024mhz = 1_024_000,
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Range768khz = 768_000,
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Range400khz = 400_000,
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Range200khz = 200_000,
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Range133khz = 133_000,
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Range100khz = 100_000,
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}
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impl Into<u32> for MSIRange {
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fn into(self) -> u32 {
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self as u32
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}
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}
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impl Into<Msirange> for MSIRange {
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fn into(self) -> Msirange {
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match self {
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MSIRange::Range48mhz => Msirange::RANGE_48MHZ,
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MSIRange::Range24mhz => Msirange::RANGE_24MHZ,
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MSIRange::Range16mhz => Msirange::RANGE_16MHZ,
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MSIRange::Range12mhz => Msirange::RANGE_12MHZ,
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MSIRange::Range4mhz => Msirange::RANGE_4MHZ,
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MSIRange::Range2mhz => Msirange::RANGE_2MHZ,
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MSIRange::Range1_33mhz => Msirange::RANGE_1_33MHZ,
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MSIRange::Range1mhz => Msirange::RANGE_1MHZ,
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MSIRange::Range3_072mhz => Msirange::RANGE_3_072MHZ,
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MSIRange::Range1_536mhz => Msirange::RANGE_1_536MHZ,
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MSIRange::Range1_024mhz => Msirange::RANGE_1_024MHZ,
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MSIRange::Range768khz => Msirange::RANGE_768KHZ,
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MSIRange::Range400khz => Msirange::RANGE_400KHZ,
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MSIRange::Range200khz => Msirange::RANGE_200KHZ,
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MSIRange::Range133khz => Msirange::RANGE_133KHZ,
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MSIRange::Range100khz => Msirange::RANGE_100KHZ,
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}
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}
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}
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impl Default for MSIRange {
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fn default() -> Self {
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MSIRange::Range4mhz
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}
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}
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#[derive(Copy, Clone)]
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pub struct Config {
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mux: ClockSrc,
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ahb_pre: AHBPrescaler,
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apb1_pre: APBPrescaler,
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apb2_pre: APBPrescaler,
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apb3_pre: APBPrescaler,
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}
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impl Config {
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pub fn new() -> Self {
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Config {}
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Config {
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mux: ClockSrc::MSI(MSIRange::default()),
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ahb_pre: Default::default(),
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apb1_pre: Default::default(),
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apb2_pre: Default::default(),
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apb3_pre: Default::default(),
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}
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}
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}
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@ -12,4 +299,218 @@ impl Default for Config {
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}
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}
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pub unsafe fn init(_config: Config) {}
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/// Extension trait that freezes the `RCC` peripheral with provided clocks configuration
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pub trait RccExt {
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fn freeze(self, config: Config, power: &Power) -> Clocks;
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}
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impl RccExt for RCC {
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#[inline]
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fn freeze(self, cfgr: Config, power: &Power) -> Clocks {
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let rcc = pac::RCC;
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let sys_clk = match cfgr.mux {
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ClockSrc::MSI(range) => {
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unsafe {
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rcc.icscr1().modify(|w| {
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let bits: Msirange = range.into();
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w.set_msisrange(bits);
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w.set_msirgsel(Msirgsel::RCC_ICSCR1);
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});
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rcc.cr().write(|w| {
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w.set_msipllen(false);
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w.set_msison(true);
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w.set_msison(true);
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});
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while !rcc.cr().read().msisrdy() {}
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}
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range.into()
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}
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ClockSrc::HSE(freq) => {
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unsafe {
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rcc.cr().write(|w| w.set_hseon(true));
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while !rcc.cr().read().hserdy() {}
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}
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freq.0
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}
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ClockSrc::HSI16 => {
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unsafe {
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rcc.cr().write(|w| w.set_hsion(true));
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while !rcc.cr().read().hsirdy() {}
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}
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HSI16_FREQ
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}
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ClockSrc::PLL1R(src, m, n, div) => {
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let freq = match src {
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PllSrc::MSI(_) => MSIRange::default().into(),
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PllSrc::HSE(hertz) => hertz.0,
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PllSrc::HSI16 => HSI16_FREQ,
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};
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// disable
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unsafe {
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rcc.cr().modify(|w| w.set_pllon(0, false));
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while rcc.cr().read().pllrdy(0) {}
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}
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let vco = freq * n as u8 as u32;
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let pll_ck = vco / (div as u8 as u32 + 1);
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unsafe {
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rcc.pll1cfgr().write(|w| {
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w.set_pllm(m.into());
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w.set_pllsrc(src.into());
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});
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rcc.pll1divr().modify(|w| {
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w.set_pllr(div.to_div());
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w.set_plln(n.to_mul());
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});
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// Enable PLL
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rcc.cr().modify(|w| w.set_pllon(0, true));
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while !rcc.cr().read().pllrdy(0) {}
|
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rcc.pll1cfgr().modify(|w| w.set_pllren(true));
|
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}
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|
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unsafe {
|
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rcc.cr().write(|w| w.set_pllon(0, true));
|
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while !rcc.cr().read().pllrdy(0) {}
|
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}
|
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|
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pll_ck
|
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}
|
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};
|
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|
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// states and programming delay
|
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let wait_states = match power.vos {
|
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// VOS 0 range VCORE 1.26V - 1.40V
|
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VoltageScale::Range1 => {
|
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if sys_clk < 32_000_000 {
|
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0
|
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} else if sys_clk < 64_000_000 {
|
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1
|
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} else if sys_clk < 96_000_000 {
|
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2
|
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} else if sys_clk < 128_000_000 {
|
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3
|
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} else {
|
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4
|
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}
|
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}
|
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// VOS 1 range VCORE 1.15V - 1.26V
|
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VoltageScale::Range2 => {
|
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if sys_clk < 30_000_000 {
|
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0
|
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} else if sys_clk < 60_000_000 {
|
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1
|
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} else if sys_clk < 90_000_000 {
|
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2
|
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} else {
|
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3
|
||||
}
|
||||
}
|
||||
// VOS 2 range VCORE 1.05V - 1.15V
|
||||
VoltageScale::Range3 => {
|
||||
if sys_clk < 24_000_000 {
|
||||
0
|
||||
} else if sys_clk < 48_000_000 {
|
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1
|
||||
} else {
|
||||
2
|
||||
}
|
||||
}
|
||||
// VOS 3 range VCORE 0.95V - 1.05V
|
||||
VoltageScale::Range4 => {
|
||||
if sys_clk < 12_000_000 {
|
||||
0
|
||||
} else {
|
||||
1
|
||||
}
|
||||
}
|
||||
};
|
||||
|
||||
unsafe {
|
||||
pac::FLASH.acr().modify(|w| {
|
||||
w.set_latency(wait_states);
|
||||
})
|
||||
}
|
||||
|
||||
unsafe {
|
||||
rcc.cfgr1().modify(|w| {
|
||||
w.set_sw(cfgr.mux.into());
|
||||
});
|
||||
|
||||
rcc.cfgr2().modify(|w| {
|
||||
w.set_hpre(cfgr.ahb_pre.into());
|
||||
w.set_ppre1(cfgr.apb1_pre.into());
|
||||
w.set_ppre2(cfgr.apb2_pre.into());
|
||||
});
|
||||
|
||||
rcc.cfgr3().modify(|w| {
|
||||
w.set_ppre3(cfgr.apb3_pre.into());
|
||||
});
|
||||
}
|
||||
|
||||
let ahb_freq: u32 = match cfgr.ahb_pre {
|
||||
AHBPrescaler::NotDivided => sys_clk,
|
||||
pre => {
|
||||
let pre: u8 = pre.into();
|
||||
let pre = 1 << (pre as u32 - 7);
|
||||
sys_clk / pre
|
||||
}
|
||||
};
|
||||
|
||||
let (apb1_freq, apb1_tim_freq) = match cfgr.apb1_pre {
|
||||
APBPrescaler::NotDivided => (ahb_freq, ahb_freq),
|
||||
pre => {
|
||||
let pre: u8 = pre.into();
|
||||
let pre: u8 = 1 << (pre - 3);
|
||||
let freq = ahb_freq / pre as u32;
|
||||
(freq, freq * 2)
|
||||
}
|
||||
};
|
||||
|
||||
let (apb2_freq, apb2_tim_freq) = match cfgr.apb2_pre {
|
||||
APBPrescaler::NotDivided => (ahb_freq, ahb_freq),
|
||||
pre => {
|
||||
let pre: u8 = pre.into();
|
||||
let pre: u8 = 1 << (pre - 3);
|
||||
let freq = ahb_freq / (1 << (pre as u8 - 3));
|
||||
(freq, freq * 2)
|
||||
}
|
||||
};
|
||||
|
||||
let (apb3_freq, _apb3_tim_freq) = match cfgr.apb3_pre {
|
||||
APBPrescaler::NotDivided => (ahb_freq, ahb_freq),
|
||||
pre => {
|
||||
let pre: u8 = pre.into();
|
||||
let pre: u8 = 1 << (pre - 3);
|
||||
let freq = ahb_freq / (1 << (pre as u8 - 3));
|
||||
(freq, freq * 2)
|
||||
}
|
||||
};
|
||||
|
||||
Clocks {
|
||||
sys: sys_clk.hz(),
|
||||
ahb1: ahb_freq.hz(),
|
||||
ahb2: ahb_freq.hz(),
|
||||
ahb3: ahb_freq.hz(),
|
||||
apb1: apb1_freq.hz(),
|
||||
apb2: apb2_freq.hz(),
|
||||
apb3: apb3_freq.hz(),
|
||||
apb1_tim: apb1_tim_freq.hz(),
|
||||
apb2_tim: apb2_tim_freq.hz(),
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
pub unsafe fn init(config: Config) {
|
||||
let r = <peripherals::RCC as embassy::util::Steal>::steal();
|
||||
let power = Power::new(<peripherals::PWR as embassy::util::Steal>::steal());
|
||||
let clocks = r.freeze(config, &power);
|
||||
set_freqs(clocks);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,6 +1,7 @@
|
|||
[target.'cfg(all(target_arch = "arm", target_os = "none"))']
|
||||
# replace STM32F429ZITx with your chip as listed in `probe-run --list-chips`
|
||||
runner = "probe-run --chip STM32U585AIIx"
|
||||
#runner = "probe-run --chip STM32U585AIIx"
|
||||
runner = "/Users/bob/outboard-repos/probe-run/target/debug/probe-run-rp --chip STM32U585AIIx"
|
||||
|
||||
[build]
|
||||
target = "thumbv7em-none-eabi"
|
||||
|
|
|
|||
|
|
@ -22,8 +22,8 @@ embassy-traits = { version = "0.1.0", path = "../../embassy-traits", features =
|
|||
embassy-stm32 = { version = "0.1.0", path = "../../embassy-stm32", features = ["defmt", "defmt-trace", "unstable-pac", "stm32u585ai", "memory-x" ] }
|
||||
embassy-hal-common = {version = "0.1.0", path = "../../embassy-hal-common" }
|
||||
|
||||
defmt = "0.2.3"
|
||||
defmt-rtt = "0.2.0"
|
||||
defmt = "0.2"
|
||||
defmt-rtt = "0.2"
|
||||
|
||||
cortex-m = "0.7.3"
|
||||
cortex-m-rt = "0.7.0"
|
||||
|
|
@ -35,3 +35,7 @@ heapless = { version = "0.7.5", default-features = false }
|
|||
|
||||
micromath = "2.0.0"
|
||||
|
||||
#[patch.crates-io]
|
||||
#defmt = { git="https://github.com/knurling-rs/defmt.git" }
|
||||
#defmt-rtt = { git="https://github.com/knurling-rs/defmt.git" }
|
||||
|
||||
|
|
|
|||
|
|
@ -1 +1 @@
|
|||
Subproject commit e106785ebae82f43c4abd33b9a3f3ea3b31d6088
|
||||
Subproject commit 103d86c0558b5ce90ab4765f87b5e756b55312f7
|
||||
Loading…
Reference in a new issue