1085 lines
32 KiB
Rust
1085 lines
32 KiB
Rust
#![macro_use]
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use core::future::poll_fn;
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use core::marker::PhantomData;
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use core::task::Poll;
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use atomic_polyfill::{compiler_fence, Ordering};
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use embassy_cortex_m::interrupt::InterruptExt;
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use embassy_futures::select::{select, Either};
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use embassy_hal_common::drop::OnDrop;
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use embassy_hal_common::{into_ref, PeripheralRef};
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use crate::dma::NoDma;
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use crate::gpio::sealed::AFType;
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#[cfg(any(lpuart_v1, lpuart_v2))]
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use crate::pac::lpuart::{regs, vals, Lpuart as Regs};
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#[cfg(not(any(lpuart_v1, lpuart_v2)))]
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use crate::pac::usart::{regs, vals, Usart as Regs};
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use crate::time::Hertz;
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use crate::{peripherals, Peripheral};
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#[derive(Clone, Copy, PartialEq, Eq, Debug)]
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pub enum DataBits {
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DataBits8,
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DataBits9,
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}
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#[derive(Clone, Copy, PartialEq, Eq, Debug)]
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pub enum Parity {
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ParityNone,
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ParityEven,
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ParityOdd,
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}
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#[derive(Clone, Copy, PartialEq, Eq, Debug)]
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pub enum StopBits {
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#[doc = "1 stop bit"]
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STOP1,
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#[doc = "0.5 stop bits"]
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STOP0P5,
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#[doc = "2 stop bits"]
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STOP2,
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#[doc = "1.5 stop bits"]
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STOP1P5,
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}
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#[non_exhaustive]
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#[derive(Clone, Copy, PartialEq, Eq, Debug)]
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pub struct Config {
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pub baudrate: u32,
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pub data_bits: DataBits,
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pub stop_bits: StopBits,
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pub parity: Parity,
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/// if true, on read-like method, if there is a latent error pending,
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/// read will abort, the error reported and cleared
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/// if false, the error is ignored and cleared
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pub detect_previous_overrun: bool,
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}
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impl Default for Config {
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fn default() -> Self {
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Self {
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baudrate: 115200,
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data_bits: DataBits::DataBits8,
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stop_bits: StopBits::STOP1,
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parity: Parity::ParityNone,
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// historical behavior
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detect_previous_overrun: false,
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}
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}
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}
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/// Serial error
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#[derive(Debug, Eq, PartialEq, Copy, Clone)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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#[non_exhaustive]
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pub enum Error {
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/// Framing error
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Framing,
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/// Noise error
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Noise,
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/// RX buffer overrun
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Overrun,
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/// Parity check error
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Parity,
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/// Buffer too large for DMA
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BufferTooLong,
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}
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enum ReadCompletionEvent {
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// DMA Read transfer completed first
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DmaCompleted,
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// Idle line detected first
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Idle,
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}
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pub struct Uart<'d, T: BasicInstance, TxDma = NoDma, RxDma = NoDma> {
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tx: UartTx<'d, T, TxDma>,
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rx: UartRx<'d, T, RxDma>,
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}
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pub struct UartTx<'d, T: BasicInstance, TxDma = NoDma> {
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phantom: PhantomData<&'d mut T>,
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tx_dma: PeripheralRef<'d, TxDma>,
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}
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pub struct UartRx<'d, T: BasicInstance, RxDma = NoDma> {
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_peri: PeripheralRef<'d, T>,
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rx_dma: PeripheralRef<'d, RxDma>,
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detect_previous_overrun: bool,
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}
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impl<'d, T: BasicInstance, TxDma> UartTx<'d, T, TxDma> {
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/// usefull if you only want Uart Tx. It saves 1 pin and consumes a little less power
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pub fn new(
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peri: impl Peripheral<P = T> + 'd,
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tx: impl Peripheral<P = impl TxPin<T>> + 'd,
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tx_dma: impl Peripheral<P = TxDma> + 'd,
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config: Config,
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) -> Self {
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T::enable();
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T::reset();
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Self::new_inner(peri, tx, tx_dma, config)
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}
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pub fn new_with_cts(
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peri: impl Peripheral<P = T> + 'd,
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tx: impl Peripheral<P = impl TxPin<T>> + 'd,
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cts: impl Peripheral<P = impl CtsPin<T>> + 'd,
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tx_dma: impl Peripheral<P = TxDma> + 'd,
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config: Config,
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) -> Self {
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into_ref!(cts);
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T::enable();
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T::reset();
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unsafe {
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cts.set_as_af(cts.af_num(), AFType::Input);
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T::regs().cr3().write(|w| {
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w.set_ctse(true);
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});
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}
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Self::new_inner(peri, tx, tx_dma, config)
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}
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fn new_inner(
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_peri: impl Peripheral<P = T> + 'd,
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tx: impl Peripheral<P = impl TxPin<T>> + 'd,
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tx_dma: impl Peripheral<P = TxDma> + 'd,
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config: Config,
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) -> Self {
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into_ref!(_peri, tx, tx_dma);
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let r = T::regs();
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unsafe {
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tx.set_as_af(tx.af_num(), AFType::OutputPushPull);
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}
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configure(r, &config, T::frequency(), T::MULTIPLIER, false, true);
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// create state once!
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let _s = T::state();
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Self {
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tx_dma,
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phantom: PhantomData,
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}
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}
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pub async fn write(&mut self, buffer: &[u8]) -> Result<(), Error>
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where
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TxDma: crate::usart::TxDma<T>,
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{
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let ch = &mut self.tx_dma;
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let request = ch.request();
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unsafe {
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T::regs().cr3().modify(|reg| {
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reg.set_dmat(true);
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});
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}
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// If we don't assign future to a variable, the data register pointer
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// is held across an await and makes the future non-Send.
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let transfer = crate::dma::write(ch, request, buffer, tdr(T::regs()));
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transfer.await;
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Ok(())
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}
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pub fn blocking_write(&mut self, buffer: &[u8]) -> Result<(), Error> {
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unsafe {
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let r = T::regs();
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for &b in buffer {
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while !sr(r).read().txe() {}
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tdr(r).write_volatile(b);
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}
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}
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Ok(())
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}
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pub fn blocking_flush(&mut self) -> Result<(), Error> {
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unsafe {
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let r = T::regs();
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while !sr(r).read().tc() {}
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}
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Ok(())
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}
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}
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impl<'d, T: BasicInstance, RxDma> UartRx<'d, T, RxDma> {
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/// usefull if you only want Uart Rx. It saves 1 pin and consumes a little less power
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pub fn new(
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peri: impl Peripheral<P = T> + 'd,
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irq: impl Peripheral<P = T::Interrupt> + 'd,
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rx: impl Peripheral<P = impl RxPin<T>> + 'd,
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rx_dma: impl Peripheral<P = RxDma> + 'd,
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config: Config,
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) -> Self {
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T::enable();
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T::reset();
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Self::new_inner(peri, irq, rx, rx_dma, config)
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}
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pub fn new_with_rts(
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peri: impl Peripheral<P = T> + 'd,
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irq: impl Peripheral<P = T::Interrupt> + 'd,
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rx: impl Peripheral<P = impl RxPin<T>> + 'd,
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rts: impl Peripheral<P = impl RtsPin<T>> + 'd,
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rx_dma: impl Peripheral<P = RxDma> + 'd,
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config: Config,
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) -> Self {
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into_ref!(rts);
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T::enable();
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T::reset();
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unsafe {
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rts.set_as_af(rts.af_num(), AFType::OutputPushPull);
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T::regs().cr3().write(|w| {
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w.set_rtse(true);
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});
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}
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Self::new_inner(peri, irq, rx, rx_dma, config)
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}
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fn new_inner(
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peri: impl Peripheral<P = T> + 'd,
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irq: impl Peripheral<P = T::Interrupt> + 'd,
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rx: impl Peripheral<P = impl RxPin<T>> + 'd,
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rx_dma: impl Peripheral<P = RxDma> + 'd,
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config: Config,
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) -> Self {
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into_ref!(peri, irq, rx, rx_dma);
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let r = T::regs();
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unsafe {
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rx.set_as_af(rx.af_num(), AFType::Input);
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}
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configure(r, &config, T::frequency(), T::MULTIPLIER, true, false);
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irq.set_handler(Self::on_interrupt);
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irq.unpend();
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irq.enable();
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// create state once!
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let _s = T::state();
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Self {
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_peri: peri,
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rx_dma,
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detect_previous_overrun: config.detect_previous_overrun,
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}
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}
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fn on_interrupt(_: *mut ()) {
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let r = T::regs();
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let s = T::state();
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let (sr, cr1, cr3) = unsafe { (sr(r).read(), r.cr1().read(), r.cr3().read()) };
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let has_errors = (sr.pe() && cr1.peie()) || ((sr.fe() || sr.ne() || sr.ore()) && cr3.eie());
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if has_errors {
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// clear all interrupts and DMA Rx Request
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unsafe {
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r.cr1().modify(|w| {
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// disable RXNE interrupt
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w.set_rxneie(false);
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// disable parity interrupt
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w.set_peie(false);
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// disable idle line interrupt
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w.set_idleie(false);
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});
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r.cr3().modify(|w| {
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// disable Error Interrupt: (Frame error, Noise error, Overrun error)
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w.set_eie(false);
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// disable DMA Rx Request
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w.set_dmar(false);
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});
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}
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compiler_fence(Ordering::SeqCst);
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s.rx_waker.wake();
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} else if cr1.idleie() && sr.idle() {
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// IDLE detected: no more data will come
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unsafe {
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r.cr1().modify(|w| {
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// disable idle line detection
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w.set_idleie(false);
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});
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r.cr3().modify(|w| {
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// disable DMA Rx Request
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w.set_dmar(false);
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});
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}
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compiler_fence(Ordering::SeqCst);
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s.rx_waker.wake();
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}
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}
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pub async fn read(&mut self, buffer: &mut [u8]) -> Result<(), Error>
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where
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RxDma: crate::usart::RxDma<T>,
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{
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self.inner_read(buffer, false).await?;
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Ok(())
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}
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pub fn nb_read(&mut self) -> Result<u8, nb::Error<Error>> {
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let r = T::regs();
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unsafe {
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let sr = sr(r).read();
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if sr.pe() {
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rdr(r).read_volatile();
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Err(nb::Error::Other(Error::Parity))
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} else if sr.fe() {
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rdr(r).read_volatile();
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Err(nb::Error::Other(Error::Framing))
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} else if sr.ne() {
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rdr(r).read_volatile();
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Err(nb::Error::Other(Error::Noise))
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} else if sr.ore() {
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rdr(r).read_volatile();
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Err(nb::Error::Other(Error::Overrun))
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} else if sr.rxne() {
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Ok(rdr(r).read_volatile())
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} else {
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Err(nb::Error::WouldBlock)
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}
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}
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}
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pub fn blocking_read(&mut self, buffer: &mut [u8]) -> Result<(), Error> {
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unsafe {
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let r = T::regs();
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for b in buffer {
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loop {
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let sr = sr(r).read();
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if sr.pe() {
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rdr(r).read_volatile();
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return Err(Error::Parity);
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} else if sr.fe() {
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rdr(r).read_volatile();
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return Err(Error::Framing);
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} else if sr.ne() {
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rdr(r).read_volatile();
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return Err(Error::Noise);
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} else if sr.ore() {
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rdr(r).read_volatile();
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return Err(Error::Overrun);
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} else if sr.rxne() {
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break;
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}
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}
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*b = rdr(r).read_volatile();
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}
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}
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Ok(())
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}
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pub async fn read_until_idle(&mut self, buffer: &mut [u8]) -> Result<usize, Error>
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where
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RxDma: crate::usart::RxDma<T>,
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{
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self.inner_read(buffer, true).await
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}
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async fn inner_read_run(
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&mut self,
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buffer: &mut [u8],
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enable_idle_line_detection: bool,
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) -> Result<ReadCompletionEvent, Error>
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where
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RxDma: crate::usart::RxDma<T>,
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{
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let r = T::regs();
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// make sure USART state is restored to neutral state when this future is dropped
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let _drop = OnDrop::new(move || {
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// defmt::trace!("Clear all USART interrupts and DMA Read Request");
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// clear all interrupts and DMA Rx Request
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// SAFETY: only clears Rx related flags
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unsafe {
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r.cr1().modify(|w| {
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// disable RXNE interrupt
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w.set_rxneie(false);
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// disable parity interrupt
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w.set_peie(false);
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// disable idle line interrupt
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w.set_idleie(false);
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});
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r.cr3().modify(|w| {
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// disable Error Interrupt: (Frame error, Noise error, Overrun error)
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w.set_eie(false);
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// disable DMA Rx Request
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w.set_dmar(false);
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});
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}
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});
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let ch = &mut self.rx_dma;
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let request = ch.request();
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// Start USART DMA
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// will not do anything yet because DMAR is not yet set
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// future which will complete when DMA Read request completes
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let transfer = crate::dma::read(ch, request, rdr(T::regs()), buffer);
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// SAFETY: The only way we might have a problem is using split rx and tx
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// here we only modify or read Rx related flags, interrupts and DMA channel
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unsafe {
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// clear ORE flag just before enabling DMA Rx Request: can be mandatory for the second transfer
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if !self.detect_previous_overrun {
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let sr = sr(r).read();
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// This read also clears the error and idle interrupt flags on v1.
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rdr(r).read_volatile();
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clear_interrupt_flags(r, sr);
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}
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r.cr1().modify(|w| {
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// disable RXNE interrupt
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w.set_rxneie(false);
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// enable parity interrupt if not ParityNone
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w.set_peie(w.pce());
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});
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r.cr3().modify(|w| {
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// enable Error Interrupt: (Frame error, Noise error, Overrun error)
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w.set_eie(true);
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// enable DMA Rx Request
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w.set_dmar(true);
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});
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compiler_fence(Ordering::SeqCst);
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// In case of errors already pending when reception started, interrupts may have already been raised
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// and lead to reception abortion (Overrun error for instance). In such a case, all interrupts
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// have been disabled in interrupt handler and DMA Rx Request has been disabled.
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let cr3 = r.cr3().read();
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if !cr3.dmar() {
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// something went wrong
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// because the only way to get this flag cleared is to have an interrupt
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// DMA will be stopped when transfer is dropped
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let sr = sr(r).read();
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// This read also clears the error and idle interrupt flags on v1.
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rdr(r).read_volatile();
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clear_interrupt_flags(r, sr);
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if sr.pe() {
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return Err(Error::Parity);
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}
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if sr.fe() {
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return Err(Error::Framing);
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}
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if sr.ne() {
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return Err(Error::Noise);
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}
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if sr.ore() {
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return Err(Error::Overrun);
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}
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unreachable!();
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}
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if !enable_idle_line_detection {
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transfer.await;
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return Ok(ReadCompletionEvent::DmaCompleted);
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}
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// clear idle flag
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let sr = sr(r).read();
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// This read also clears the error and idle interrupt flags on v1.
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rdr(r).read_volatile();
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clear_interrupt_flags(r, sr);
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// enable idle interrupt
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r.cr1().modify(|w| {
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w.set_idleie(true);
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});
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}
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compiler_fence(Ordering::SeqCst);
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|
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// future which completes when idle line is detected
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let idle = poll_fn(move |cx| {
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let s = T::state();
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s.rx_waker.register(cx.waker());
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// SAFETY: read only and we only use Rx related flags
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let sr = unsafe { sr(r).read() };
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|
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// SAFETY: only clears Rx related flags
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unsafe {
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// This read also clears the error and idle interrupt flags on v1.
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rdr(r).read_volatile();
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clear_interrupt_flags(r, sr);
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}
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|
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compiler_fence(Ordering::SeqCst);
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let has_errors = sr.pe() || sr.fe() || sr.ne() || sr.ore();
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|
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if has_errors {
|
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// all Rx interrupts and Rx DMA Request have already been cleared in interrupt handler
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|
|
|
if sr.pe() {
|
|
return Poll::Ready(Err(Error::Parity));
|
|
}
|
|
if sr.fe() {
|
|
return Poll::Ready(Err(Error::Framing));
|
|
}
|
|
if sr.ne() {
|
|
return Poll::Ready(Err(Error::Noise));
|
|
}
|
|
if sr.ore() {
|
|
return Poll::Ready(Err(Error::Overrun));
|
|
}
|
|
}
|
|
|
|
if sr.idle() {
|
|
// Idle line detected
|
|
return Poll::Ready(Ok(()));
|
|
}
|
|
|
|
Poll::Pending
|
|
});
|
|
|
|
// wait for the first of DMA request or idle line detected to completes
|
|
// select consumes its arguments
|
|
// when transfer is dropped, it will stop the DMA request
|
|
match select(transfer, idle).await {
|
|
// DMA transfer completed first
|
|
Either::First(()) => Ok(ReadCompletionEvent::DmaCompleted),
|
|
|
|
// Idle line detected first
|
|
Either::Second(Ok(())) => Ok(ReadCompletionEvent::Idle),
|
|
|
|
// error occurred
|
|
Either::Second(Err(e)) => Err(e),
|
|
}
|
|
}
|
|
|
|
async fn inner_read(&mut self, buffer: &mut [u8], enable_idle_line_detection: bool) -> Result<usize, Error>
|
|
where
|
|
RxDma: crate::usart::RxDma<T>,
|
|
{
|
|
if buffer.is_empty() {
|
|
return Ok(0);
|
|
} else if buffer.len() > 0xFFFF {
|
|
return Err(Error::BufferTooLong);
|
|
}
|
|
|
|
let buffer_len = buffer.len();
|
|
|
|
// wait for DMA to complete or IDLE line detection if requested
|
|
let res = self.inner_read_run(buffer, enable_idle_line_detection).await;
|
|
|
|
let ch = &mut self.rx_dma;
|
|
|
|
match res {
|
|
Ok(ReadCompletionEvent::DmaCompleted) => Ok(buffer_len),
|
|
Ok(ReadCompletionEvent::Idle) => {
|
|
let n = buffer_len - (ch.remaining_transfers() as usize);
|
|
Ok(n)
|
|
}
|
|
Err(e) => Err(e),
|
|
}
|
|
}
|
|
}
|
|
|
|
impl<'d, T: BasicInstance, TxDma, RxDma> Uart<'d, T, TxDma, RxDma> {
|
|
pub fn new(
|
|
peri: impl Peripheral<P = T> + 'd,
|
|
rx: impl Peripheral<P = impl RxPin<T>> + 'd,
|
|
tx: impl Peripheral<P = impl TxPin<T>> + 'd,
|
|
irq: impl Peripheral<P = T::Interrupt> + 'd,
|
|
tx_dma: impl Peripheral<P = TxDma> + 'd,
|
|
rx_dma: impl Peripheral<P = RxDma> + 'd,
|
|
config: Config,
|
|
) -> Self {
|
|
T::enable();
|
|
T::reset();
|
|
|
|
Self::new_inner(peri, rx, tx, irq, tx_dma, rx_dma, config)
|
|
}
|
|
|
|
pub fn new_with_rtscts(
|
|
peri: impl Peripheral<P = T> + 'd,
|
|
rx: impl Peripheral<P = impl RxPin<T>> + 'd,
|
|
tx: impl Peripheral<P = impl TxPin<T>> + 'd,
|
|
irq: impl Peripheral<P = T::Interrupt> + 'd,
|
|
rts: impl Peripheral<P = impl RtsPin<T>> + 'd,
|
|
cts: impl Peripheral<P = impl CtsPin<T>> + 'd,
|
|
tx_dma: impl Peripheral<P = TxDma> + 'd,
|
|
rx_dma: impl Peripheral<P = RxDma> + 'd,
|
|
config: Config,
|
|
) -> Self {
|
|
into_ref!(cts, rts);
|
|
|
|
T::enable();
|
|
T::reset();
|
|
|
|
unsafe {
|
|
rts.set_as_af(rts.af_num(), AFType::OutputPushPull);
|
|
cts.set_as_af(cts.af_num(), AFType::Input);
|
|
T::regs().cr3().write(|w| {
|
|
w.set_rtse(true);
|
|
w.set_ctse(true);
|
|
});
|
|
}
|
|
Self::new_inner(peri, rx, tx, irq, tx_dma, rx_dma, config)
|
|
}
|
|
|
|
fn new_inner(
|
|
peri: impl Peripheral<P = T> + 'd,
|
|
rx: impl Peripheral<P = impl RxPin<T>> + 'd,
|
|
tx: impl Peripheral<P = impl TxPin<T>> + 'd,
|
|
irq: impl Peripheral<P = T::Interrupt> + 'd,
|
|
tx_dma: impl Peripheral<P = TxDma> + 'd,
|
|
rx_dma: impl Peripheral<P = RxDma> + 'd,
|
|
config: Config,
|
|
) -> Self {
|
|
into_ref!(peri, rx, tx, irq, tx_dma, rx_dma);
|
|
|
|
let r = T::regs();
|
|
|
|
unsafe {
|
|
rx.set_as_af(rx.af_num(), AFType::Input);
|
|
tx.set_as_af(tx.af_num(), AFType::OutputPushPull);
|
|
}
|
|
|
|
configure(r, &config, T::frequency(), T::MULTIPLIER, true, true);
|
|
|
|
irq.set_handler(UartRx::<T, RxDma>::on_interrupt);
|
|
irq.unpend();
|
|
irq.enable();
|
|
|
|
// create state once!
|
|
let _s = T::state();
|
|
|
|
Self {
|
|
tx: UartTx {
|
|
tx_dma,
|
|
phantom: PhantomData,
|
|
},
|
|
rx: UartRx {
|
|
_peri: peri,
|
|
rx_dma,
|
|
detect_previous_overrun: config.detect_previous_overrun,
|
|
},
|
|
}
|
|
}
|
|
|
|
pub async fn write(&mut self, buffer: &[u8]) -> Result<(), Error>
|
|
where
|
|
TxDma: crate::usart::TxDma<T>,
|
|
{
|
|
self.tx.write(buffer).await
|
|
}
|
|
|
|
pub fn blocking_write(&mut self, buffer: &[u8]) -> Result<(), Error> {
|
|
self.tx.blocking_write(buffer)
|
|
}
|
|
|
|
pub fn blocking_flush(&mut self) -> Result<(), Error> {
|
|
self.tx.blocking_flush()
|
|
}
|
|
|
|
pub async fn read(&mut self, buffer: &mut [u8]) -> Result<(), Error>
|
|
where
|
|
RxDma: crate::usart::RxDma<T>,
|
|
{
|
|
self.rx.read(buffer).await
|
|
}
|
|
|
|
pub fn nb_read(&mut self) -> Result<u8, nb::Error<Error>> {
|
|
self.rx.nb_read()
|
|
}
|
|
|
|
pub fn blocking_read(&mut self, buffer: &mut [u8]) -> Result<(), Error> {
|
|
self.rx.blocking_read(buffer)
|
|
}
|
|
|
|
pub async fn read_until_idle(&mut self, buffer: &mut [u8]) -> Result<usize, Error>
|
|
where
|
|
RxDma: crate::usart::RxDma<T>,
|
|
{
|
|
self.rx.read_until_idle(buffer).await
|
|
}
|
|
|
|
/// Split the Uart into a transmitter and receiver, which is
|
|
/// particuarly useful when having two tasks correlating to
|
|
/// transmitting and receiving.
|
|
pub fn split(self) -> (UartTx<'d, T, TxDma>, UartRx<'d, T, RxDma>) {
|
|
(self.tx, self.rx)
|
|
}
|
|
}
|
|
|
|
fn configure(r: Regs, config: &Config, pclk_freq: Hertz, multiplier: u32, enable_rx: bool, enable_tx: bool) {
|
|
if !enable_rx && !enable_tx {
|
|
panic!("USART: At least one of RX or TX should be enabled");
|
|
}
|
|
|
|
// TODO: better calculation, including error checking and OVER8 if possible.
|
|
let div = (pclk_freq.0 + (config.baudrate / 2)) / config.baudrate * multiplier;
|
|
|
|
unsafe {
|
|
r.brr().write_value(regs::Brr(div));
|
|
r.cr2().write(|_w| {});
|
|
r.cr1().write(|w| {
|
|
// enable uart
|
|
w.set_ue(true);
|
|
// enable transceiver
|
|
w.set_te(enable_tx);
|
|
// enable receiver
|
|
w.set_re(enable_rx);
|
|
// configure word size
|
|
w.set_m0(if config.parity != Parity::ParityNone {
|
|
vals::M0::BIT9
|
|
} else {
|
|
vals::M0::BIT8
|
|
});
|
|
// configure parity
|
|
w.set_pce(config.parity != Parity::ParityNone);
|
|
w.set_ps(match config.parity {
|
|
Parity::ParityOdd => vals::Ps::ODD,
|
|
Parity::ParityEven => vals::Ps::EVEN,
|
|
_ => vals::Ps::EVEN,
|
|
});
|
|
});
|
|
}
|
|
}
|
|
|
|
mod eh02 {
|
|
use super::*;
|
|
|
|
impl<'d, T: BasicInstance, RxDma> embedded_hal_02::serial::Read<u8> for UartRx<'d, T, RxDma> {
|
|
type Error = Error;
|
|
fn read(&mut self) -> Result<u8, nb::Error<Self::Error>> {
|
|
self.nb_read()
|
|
}
|
|
}
|
|
|
|
impl<'d, T: BasicInstance, TxDma> embedded_hal_02::blocking::serial::Write<u8> for UartTx<'d, T, TxDma> {
|
|
type Error = Error;
|
|
fn bwrite_all(&mut self, buffer: &[u8]) -> Result<(), Self::Error> {
|
|
self.blocking_write(buffer)
|
|
}
|
|
fn bflush(&mut self) -> Result<(), Self::Error> {
|
|
self.blocking_flush()
|
|
}
|
|
}
|
|
|
|
impl<'d, T: BasicInstance, TxDma, RxDma> embedded_hal_02::serial::Read<u8> for Uart<'d, T, TxDma, RxDma> {
|
|
type Error = Error;
|
|
fn read(&mut self) -> Result<u8, nb::Error<Self::Error>> {
|
|
self.nb_read()
|
|
}
|
|
}
|
|
|
|
impl<'d, T: BasicInstance, TxDma, RxDma> embedded_hal_02::blocking::serial::Write<u8> for Uart<'d, T, TxDma, RxDma> {
|
|
type Error = Error;
|
|
fn bwrite_all(&mut self, buffer: &[u8]) -> Result<(), Self::Error> {
|
|
self.blocking_write(buffer)
|
|
}
|
|
fn bflush(&mut self) -> Result<(), Self::Error> {
|
|
self.blocking_flush()
|
|
}
|
|
}
|
|
}
|
|
|
|
#[cfg(feature = "unstable-traits")]
|
|
mod eh1 {
|
|
use super::*;
|
|
|
|
impl embedded_hal_1::serial::Error for Error {
|
|
fn kind(&self) -> embedded_hal_1::serial::ErrorKind {
|
|
match *self {
|
|
Self::Framing => embedded_hal_1::serial::ErrorKind::FrameFormat,
|
|
Self::Noise => embedded_hal_1::serial::ErrorKind::Noise,
|
|
Self::Overrun => embedded_hal_1::serial::ErrorKind::Overrun,
|
|
Self::Parity => embedded_hal_1::serial::ErrorKind::Parity,
|
|
Self::BufferTooLong => embedded_hal_1::serial::ErrorKind::Other,
|
|
}
|
|
}
|
|
}
|
|
|
|
impl<'d, T: BasicInstance, TxDma, RxDma> embedded_hal_1::serial::ErrorType for Uart<'d, T, TxDma, RxDma> {
|
|
type Error = Error;
|
|
}
|
|
|
|
impl<'d, T: BasicInstance, TxDma> embedded_hal_1::serial::ErrorType for UartTx<'d, T, TxDma> {
|
|
type Error = Error;
|
|
}
|
|
|
|
impl<'d, T: BasicInstance, RxDma> embedded_hal_1::serial::ErrorType for UartRx<'d, T, RxDma> {
|
|
type Error = Error;
|
|
}
|
|
|
|
impl<'d, T: BasicInstance, RxDma> embedded_hal_nb::serial::Read for UartRx<'d, T, RxDma> {
|
|
fn read(&mut self) -> nb::Result<u8, Self::Error> {
|
|
self.nb_read()
|
|
}
|
|
}
|
|
|
|
impl<'d, T: BasicInstance, TxDma> embedded_hal_1::serial::Write for UartTx<'d, T, TxDma> {
|
|
fn write(&mut self, buffer: &[u8]) -> Result<(), Self::Error> {
|
|
self.blocking_write(buffer)
|
|
}
|
|
|
|
fn flush(&mut self) -> Result<(), Self::Error> {
|
|
self.blocking_flush()
|
|
}
|
|
}
|
|
|
|
impl<'d, T: BasicInstance, TxDma> embedded_hal_nb::serial::Write for UartTx<'d, T, TxDma> {
|
|
fn write(&mut self, char: u8) -> nb::Result<(), Self::Error> {
|
|
self.blocking_write(&[char]).map_err(nb::Error::Other)
|
|
}
|
|
|
|
fn flush(&mut self) -> nb::Result<(), Self::Error> {
|
|
self.blocking_flush().map_err(nb::Error::Other)
|
|
}
|
|
}
|
|
|
|
impl<'d, T: BasicInstance, TxDma, RxDma> embedded_hal_nb::serial::Read for Uart<'d, T, TxDma, RxDma> {
|
|
fn read(&mut self) -> Result<u8, nb::Error<Self::Error>> {
|
|
self.nb_read()
|
|
}
|
|
}
|
|
|
|
impl<'d, T: BasicInstance, TxDma, RxDma> embedded_hal_1::serial::Write for Uart<'d, T, TxDma, RxDma> {
|
|
fn write(&mut self, buffer: &[u8]) -> Result<(), Self::Error> {
|
|
self.blocking_write(buffer)
|
|
}
|
|
|
|
fn flush(&mut self) -> Result<(), Self::Error> {
|
|
self.blocking_flush()
|
|
}
|
|
}
|
|
|
|
impl<'d, T: BasicInstance, TxDma, RxDma> embedded_hal_nb::serial::Write for Uart<'d, T, TxDma, RxDma> {
|
|
fn write(&mut self, char: u8) -> nb::Result<(), Self::Error> {
|
|
self.blocking_write(&[char]).map_err(nb::Error::Other)
|
|
}
|
|
|
|
fn flush(&mut self) -> nb::Result<(), Self::Error> {
|
|
self.blocking_flush().map_err(nb::Error::Other)
|
|
}
|
|
}
|
|
}
|
|
|
|
#[cfg(all(
|
|
feature = "unstable-traits",
|
|
feature = "nightly",
|
|
feature = "_todo_embedded_hal_serial"
|
|
))]
|
|
mod eha {
|
|
use core::future::Future;
|
|
|
|
use super::*;
|
|
|
|
impl<'d, T: BasicInstance, TxDma> embedded_hal_async::serial::Write for UartTx<'d, T, TxDma>
|
|
where
|
|
TxDma: crate::usart::TxDma<T>,
|
|
{
|
|
type WriteFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a;
|
|
|
|
fn write<'a>(&'a mut self, buf: &'a [u8]) -> Self::WriteFuture<'a> {
|
|
self.write(buf)
|
|
}
|
|
|
|
type FlushFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a;
|
|
|
|
fn flush<'a>(&'a mut self) -> Self::FlushFuture<'a> {
|
|
async move { Ok(()) }
|
|
}
|
|
}
|
|
|
|
impl<'d, T: BasicInstance, RxDma> embedded_hal_async::serial::Read for UartRx<'d, T, RxDma>
|
|
where
|
|
RxDma: crate::usart::RxDma<T>,
|
|
{
|
|
type ReadFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a;
|
|
|
|
fn read<'a>(&'a mut self, buf: &'a mut [u8]) -> Self::ReadFuture<'a> {
|
|
self.read(buf)
|
|
}
|
|
}
|
|
|
|
impl<'d, T: BasicInstance, TxDma, RxDma> embedded_hal_async::serial::Write for Uart<'d, T, TxDma, RxDma>
|
|
where
|
|
TxDma: crate::usart::TxDma<T>,
|
|
{
|
|
type WriteFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a;
|
|
|
|
fn write<'a>(&'a mut self, buf: &'a [u8]) -> Self::WriteFuture<'a> {
|
|
self.write(buf)
|
|
}
|
|
|
|
type FlushFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a;
|
|
|
|
fn flush<'a>(&'a mut self) -> Self::FlushFuture<'a> {
|
|
async move { Ok(()) }
|
|
}
|
|
}
|
|
|
|
impl<'d, T: BasicInstance, TxDma, RxDma> embedded_hal_async::serial::Read for Uart<'d, T, TxDma, RxDma>
|
|
where
|
|
RxDma: crate::usart::RxDma<T>,
|
|
{
|
|
type ReadFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a;
|
|
|
|
fn read<'a>(&'a mut self, buf: &'a mut [u8]) -> Self::ReadFuture<'a> {
|
|
self.read(buf)
|
|
}
|
|
}
|
|
}
|
|
|
|
#[cfg(feature = "nightly")]
|
|
pub use buffered::*;
|
|
#[cfg(feature = "nightly")]
|
|
mod buffered;
|
|
|
|
#[cfg(usart_v1)]
|
|
fn tdr(r: crate::pac::usart::Usart) -> *mut u8 {
|
|
r.dr().ptr() as _
|
|
}
|
|
|
|
#[cfg(usart_v1)]
|
|
fn rdr(r: crate::pac::usart::Usart) -> *mut u8 {
|
|
r.dr().ptr() as _
|
|
}
|
|
|
|
#[cfg(usart_v1)]
|
|
fn sr(r: crate::pac::usart::Usart) -> crate::pac::common::Reg<regs::Sr, crate::pac::common::RW> {
|
|
r.sr()
|
|
}
|
|
|
|
#[cfg(usart_v1)]
|
|
#[allow(unused)]
|
|
unsafe fn clear_interrupt_flags(_r: Regs, _sr: regs::Sr) {
|
|
// On v1 the flags are cleared implicitly by reads and writes to DR.
|
|
}
|
|
|
|
#[cfg(usart_v2)]
|
|
fn tdr(r: Regs) -> *mut u8 {
|
|
r.tdr().ptr() as _
|
|
}
|
|
|
|
#[cfg(usart_v2)]
|
|
fn rdr(r: Regs) -> *mut u8 {
|
|
r.rdr().ptr() as _
|
|
}
|
|
|
|
#[cfg(usart_v2)]
|
|
fn sr(r: Regs) -> crate::pac::common::Reg<regs::Isr, crate::pac::common::R> {
|
|
r.isr()
|
|
}
|
|
|
|
#[cfg(usart_v2)]
|
|
#[allow(unused)]
|
|
unsafe fn clear_interrupt_flags(r: Regs, sr: regs::Isr) {
|
|
r.icr().write(|w| *w = regs::Icr(sr.0));
|
|
}
|
|
|
|
pub(crate) mod sealed {
|
|
use embassy_sync::waitqueue::AtomicWaker;
|
|
|
|
use super::*;
|
|
|
|
pub struct State {
|
|
pub rx_waker: AtomicWaker,
|
|
pub tx_waker: AtomicWaker,
|
|
}
|
|
|
|
impl State {
|
|
pub const fn new() -> Self {
|
|
Self {
|
|
rx_waker: AtomicWaker::new(),
|
|
tx_waker: AtomicWaker::new(),
|
|
}
|
|
}
|
|
}
|
|
|
|
pub trait BasicInstance: crate::rcc::RccPeripheral {
|
|
const MULTIPLIER: u32;
|
|
type Interrupt: crate::interrupt::Interrupt;
|
|
|
|
fn regs() -> Regs;
|
|
fn state() -> &'static State;
|
|
}
|
|
|
|
pub trait FullInstance: BasicInstance {
|
|
fn regs_uart() -> crate::pac::usart::Usart;
|
|
}
|
|
}
|
|
|
|
pub trait BasicInstance: Peripheral<P = Self> + sealed::BasicInstance + 'static + Send {}
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pub trait FullInstance: sealed::FullInstance {}
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pin_trait!(RxPin, BasicInstance);
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pin_trait!(TxPin, BasicInstance);
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pin_trait!(CtsPin, BasicInstance);
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pin_trait!(RtsPin, BasicInstance);
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pin_trait!(CkPin, BasicInstance);
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dma_trait!(TxDma, BasicInstance);
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dma_trait!(RxDma, BasicInstance);
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macro_rules! impl_lpuart {
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($inst:ident, $irq:ident, $mul:expr) => {
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impl sealed::BasicInstance for crate::peripherals::$inst {
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const MULTIPLIER: u32 = $mul;
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type Interrupt = crate::interrupt::$irq;
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fn regs() -> Regs {
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Regs(crate::pac::$inst.0)
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}
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fn state() -> &'static crate::usart::sealed::State {
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static STATE: crate::usart::sealed::State = crate::usart::sealed::State::new();
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&STATE
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}
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}
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impl BasicInstance for peripherals::$inst {}
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};
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}
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foreach_interrupt!(
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($inst:ident, lpuart, $block:ident, $signal_name:ident, $irq:ident) => {
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impl_lpuart!($inst, $irq, 255);
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};
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($inst:ident, usart, $block:ident, $signal_name:ident, $irq:ident) => {
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impl_lpuart!($inst, $irq, 1);
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impl sealed::FullInstance for peripherals::$inst {
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fn regs_uart() -> crate::pac::usart::Usart {
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crate::pac::$inst
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}
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}
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impl FullInstance for peripherals::$inst {
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}
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};
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);
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