487 lines
13 KiB
Rust
487 lines
13 KiB
Rust
#![macro_use]
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use crate::dma::NoDma;
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use crate::gpio::sealed::AFType;
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use crate::gpio::sealed::Pin;
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use crate::gpio::{AnyPin, NoPin};
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use crate::pac::spi;
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use crate::peripherals;
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use crate::spi::{
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ByteOrder, Config, Error, Instance, MisoPin, MosiPin, RxDmaChannel, SckPin, TxDmaChannel,
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WordSize,
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};
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use crate::time::Hertz;
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use core::future::Future;
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use core::marker::PhantomData;
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use core::ptr;
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use embassy::util::Unborrow;
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use embassy_hal_common::unborrow;
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use embassy_traits::spi as traits;
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pub use embedded_hal::blocking;
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pub use embedded_hal::spi::{Mode, Phase, Polarity, MODE_0, MODE_1, MODE_2, MODE_3};
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use futures::future::join3;
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impl WordSize {
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fn dff(&self) -> spi::vals::Dff {
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match self {
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WordSize::EightBit => spi::vals::Dff::EIGHTBIT,
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WordSize::SixteenBit => spi::vals::Dff::SIXTEENBIT,
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}
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}
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}
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macro_rules! impl_nopin {
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($inst:ident, $signal:ident) => {
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impl $signal<peripherals::$inst> for NoPin {}
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impl super::sealed::$signal<peripherals::$inst> for NoPin {
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fn af_num(&self) -> u8 {
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0
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}
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}
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};
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}
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crate::pac::peripherals!(
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(spi, $inst:ident) => {
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impl_nopin!($inst, SckPin);
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impl_nopin!($inst, MosiPin);
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impl_nopin!($inst, MisoPin);
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};
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);
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pub struct Spi<'d, T: Instance, Tx, Rx> {
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sck: Option<AnyPin>,
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mosi: Option<AnyPin>,
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miso: Option<AnyPin>,
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txdma: Tx,
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rxdma: Rx,
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current_word_size: WordSize,
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phantom: PhantomData<&'d mut T>,
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}
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impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
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pub fn new<F>(
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_peri: impl Unborrow<Target = T> + 'd,
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sck: impl Unborrow<Target = impl SckPin<T>>,
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mosi: impl Unborrow<Target = impl MosiPin<T>>,
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miso: impl Unborrow<Target = impl MisoPin<T>>,
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txdma: impl Unborrow<Target = Tx>,
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rxdma: impl Unborrow<Target = Rx>,
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freq: F,
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config: Config,
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) -> Self
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where
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F: Into<Hertz>,
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{
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unborrow!(sck, mosi, miso, txdma, rxdma);
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let sck_af = sck.af_num();
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let mosi_af = mosi.af_num();
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let miso_af = miso.af_num();
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let sck = sck.degrade_optional();
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let mosi = mosi.degrade_optional();
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let miso = miso.degrade_optional();
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unsafe {
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sck.as_ref()
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.map(|x| x.set_as_af(sck_af, AFType::OutputPushPull));
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mosi.as_ref()
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.map(|x| x.set_as_af(mosi_af, AFType::OutputPushPull));
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miso.as_ref().map(|x| x.set_as_af(miso_af, AFType::Input));
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}
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unsafe {
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T::regs().cr2().modify(|w| {
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w.set_ssoe(false);
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});
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}
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let pclk = T::frequency();
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let br = Self::compute_baud_rate(pclk, freq.into());
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unsafe {
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T::enable();
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T::reset();
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T::regs().cr1().modify(|w| {
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w.set_cpha(
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match config.mode.phase == Phase::CaptureOnSecondTransition {
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true => spi::vals::Cpha::SECONDEDGE,
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false => spi::vals::Cpha::FIRSTEDGE,
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},
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);
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w.set_cpol(match config.mode.polarity == Polarity::IdleHigh {
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true => spi::vals::Cpol::IDLEHIGH,
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false => spi::vals::Cpol::IDLELOW,
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});
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w.set_mstr(spi::vals::Mstr::MASTER);
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w.set_br(spi::vals::Br(br));
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w.set_spe(true);
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w.set_lsbfirst(match config.byte_order {
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ByteOrder::LsbFirst => spi::vals::Lsbfirst::LSBFIRST,
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ByteOrder::MsbFirst => spi::vals::Lsbfirst::MSBFIRST,
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});
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w.set_ssi(true);
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w.set_ssm(true);
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w.set_crcen(false);
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w.set_bidimode(spi::vals::Bidimode::UNIDIRECTIONAL);
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if mosi.is_none() {
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w.set_rxonly(spi::vals::Rxonly::OUTPUTDISABLED);
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}
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w.set_dff(WordSize::EightBit.dff())
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});
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}
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Self {
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sck,
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mosi,
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miso,
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txdma,
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rxdma,
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current_word_size: WordSize::EightBit,
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phantom: PhantomData,
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}
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}
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fn compute_baud_rate(clocks: Hertz, freq: Hertz) -> u8 {
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match clocks.0 / freq.0 {
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0 => unreachable!(),
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1..=2 => 0b000,
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3..=5 => 0b001,
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6..=11 => 0b010,
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12..=23 => 0b011,
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24..=39 => 0b100,
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40..=95 => 0b101,
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96..=191 => 0b110,
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_ => 0b111,
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}
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}
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fn set_word_size(&mut self, word_size: WordSize) {
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if self.current_word_size == word_size {
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return;
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}
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unsafe {
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T::regs().cr1().modify(|reg| {
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reg.set_spe(false);
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reg.set_dff(word_size.dff())
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});
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T::regs().cr1().modify(|reg| {
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reg.set_spe(true);
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});
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self.current_word_size = word_size;
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}
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}
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#[allow(unused)]
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async fn write_dma_u8(&mut self, write: &[u8]) -> Result<(), Error>
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where
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Tx: TxDmaChannel<T>,
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{
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unsafe {
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T::regs().cr1().modify(|w| {
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w.set_spe(false);
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});
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}
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self.set_word_size(WordSize::EightBit);
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let request = self.txdma.request();
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let dst = T::regs().dr().ptr() as *mut u8;
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let f = self.txdma.write(request, write, dst);
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unsafe {
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T::regs().cr2().modify(|reg| {
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reg.set_txdmaen(true);
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});
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T::regs().cr1().modify(|w| {
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w.set_spe(true);
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});
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}
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f.await;
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Ok(())
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}
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#[allow(unused)]
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async fn read_dma_u8(&mut self, read: &mut [u8]) -> Result<(), Error>
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where
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Tx: TxDmaChannel<T>,
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Rx: RxDmaChannel<T>,
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{
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unsafe {
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T::regs().cr1().modify(|w| {
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w.set_spe(false);
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});
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T::regs().cr2().modify(|reg| {
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reg.set_rxdmaen(true);
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});
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}
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self.set_word_size(WordSize::EightBit);
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let clock_byte_count = read.len();
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let rx_request = self.rxdma.request();
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let rx_src = T::regs().dr().ptr() as *mut u8;
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let rx_f = self.rxdma.read(rx_request, rx_src, read);
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let tx_request = self.txdma.request();
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let tx_dst = T::regs().dr().ptr() as *mut u8;
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let clock_byte = 0x00;
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let tx_f = self
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.txdma
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.write_x(tx_request, &clock_byte, clock_byte_count, tx_dst);
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unsafe {
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T::regs().cr2().modify(|reg| {
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reg.set_txdmaen(true);
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});
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T::regs().cr1().modify(|w| {
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w.set_spe(true);
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});
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}
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join3(tx_f, rx_f, Self::wait_for_idle()).await;
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unsafe {
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T::regs().cr2().modify(|reg| {
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reg.set_txdmaen(false);
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reg.set_rxdmaen(false);
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});
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T::regs().cr1().modify(|w| {
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w.set_spe(false);
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});
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}
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Ok(())
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}
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#[allow(unused)]
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async fn read_write_dma_u8(&mut self, read: &mut [u8], write: &[u8]) -> Result<(), Error>
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where
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Tx: TxDmaChannel<T>,
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Rx: RxDmaChannel<T>,
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{
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assert!(read.len() >= write.len());
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unsafe {
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T::regs().cr1().modify(|w| {
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w.set_spe(false);
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});
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T::regs().cr2().modify(|reg| {
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reg.set_rxdmaen(true);
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});
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}
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self.set_word_size(WordSize::EightBit);
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let rx_request = self.rxdma.request();
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let rx_src = T::regs().dr().ptr() as *mut u8;
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let rx_f = self
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.rxdma
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.read(rx_request, rx_src, &mut read[0..write.len()]);
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let tx_request = self.txdma.request();
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let tx_dst = T::regs().dr().ptr() as *mut u8;
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let tx_f = self.txdma.write(tx_request, write, tx_dst);
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unsafe {
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T::regs().cr2().modify(|reg| {
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reg.set_txdmaen(true);
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});
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T::regs().cr1().modify(|w| {
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w.set_spe(true);
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});
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}
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join3(tx_f, rx_f, Self::wait_for_idle()).await;
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unsafe {
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T::regs().cr2().modify(|reg| {
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reg.set_txdmaen(false);
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reg.set_rxdmaen(false);
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});
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T::regs().cr1().modify(|w| {
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w.set_spe(false);
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});
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}
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Ok(())
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}
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async fn wait_for_idle() {
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unsafe {
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while T::regs().sr().read().bsy() {
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// spin
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}
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}
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}
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}
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impl<'d, T: Instance, Tx, Rx> Drop for Spi<'d, T, Tx, Rx> {
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fn drop(&mut self) {
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unsafe {
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self.sck.as_ref().map(|x| x.set_as_analog());
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self.mosi.as_ref().map(|x| x.set_as_analog());
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self.miso.as_ref().map(|x| x.set_as_analog());
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}
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}
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}
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impl<'d, T: Instance> embedded_hal::blocking::spi::Write<u8> for Spi<'d, T, NoDma, NoDma> {
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type Error = Error;
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fn write(&mut self, words: &[u8]) -> Result<(), Self::Error> {
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self.set_word_size(WordSize::EightBit);
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let regs = T::regs();
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for word in words.iter() {
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write_word(regs, *word)?;
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let _: u8 = read_word(regs)?;
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}
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Ok(())
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}
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}
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impl<'d, T: Instance> embedded_hal::blocking::spi::Transfer<u8> for Spi<'d, T, NoDma, NoDma> {
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type Error = Error;
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fn transfer<'w>(&mut self, words: &'w mut [u8]) -> Result<&'w [u8], Self::Error> {
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self.set_word_size(WordSize::EightBit);
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let regs = T::regs();
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for word in words.iter_mut() {
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write_word(regs, *word)?;
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*word = read_word(regs)?;
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}
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Ok(words)
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}
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}
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impl<'d, T: Instance> embedded_hal::blocking::spi::Write<u16> for Spi<'d, T, NoDma, NoDma> {
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type Error = Error;
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fn write(&mut self, words: &[u16]) -> Result<(), Self::Error> {
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self.set_word_size(WordSize::SixteenBit);
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let regs = T::regs();
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for word in words.iter() {
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write_word(regs, *word)?;
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let _: u8 = read_word(regs)?;
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}
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Ok(())
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}
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}
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impl<'d, T: Instance> embedded_hal::blocking::spi::Transfer<u16> for Spi<'d, T, NoDma, NoDma> {
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type Error = Error;
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fn transfer<'w>(&mut self, words: &'w mut [u16]) -> Result<&'w [u16], Self::Error> {
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self.set_word_size(WordSize::SixteenBit);
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let regs = T::regs();
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for word in words.iter_mut() {
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write_word(regs, *word)?;
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*word = read_word(regs)?;
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}
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Ok(words)
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}
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}
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impl<'d, T: Instance, Tx, Rx> traits::Spi<u8> for Spi<'d, T, Tx, Rx> {
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type Error = super::Error;
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}
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impl<'d, T: Instance, Tx: TxDmaChannel<T>, Rx> traits::Write<u8> for Spi<'d, T, Tx, Rx> {
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#[rustfmt::skip]
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type WriteFuture<'a> where Self: 'a = impl Future<Output = Result<(), Self::Error>> + 'a;
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fn write<'a>(&'a mut self, data: &'a [u8]) -> Self::WriteFuture<'a> {
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self.write_dma_u8(data)
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}
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}
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impl<'d, T: Instance, Tx: TxDmaChannel<T>, Rx: RxDmaChannel<T>> traits::Read<u8>
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for Spi<'d, T, Tx, Rx>
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{
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#[rustfmt::skip]
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type ReadFuture<'a> where Self: 'a = impl Future<Output = Result<(), Self::Error>> + 'a;
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fn read<'a>(&'a mut self, data: &'a mut [u8]) -> Self::ReadFuture<'a> {
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self.read_dma_u8(data)
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}
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}
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impl<'d, T: Instance, Tx: TxDmaChannel<T>, Rx: RxDmaChannel<T>> traits::FullDuplex<u8>
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for Spi<'d, T, Tx, Rx>
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{
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#[rustfmt::skip]
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type WriteReadFuture<'a> where Self: 'a = impl Future<Output=Result<(), Self::Error>> + 'a;
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fn read_write<'a>(
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&'a mut self,
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read: &'a mut [u8],
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write: &'a [u8],
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) -> Self::WriteReadFuture<'a> {
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self.read_write_dma_u8(read, write)
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}
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}
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trait Word {}
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impl Word for u8 {}
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impl Word for u16 {}
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fn write_word<W: Word>(regs: &'static crate::pac::spi::Spi, word: W) -> Result<(), Error> {
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loop {
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let sr = unsafe { regs.sr().read() };
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if sr.ovr() {
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return Err(Error::Overrun);
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}
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#[cfg(not(spi_f1))]
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if sr.fre() {
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return Err(Error::Framing);
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}
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if sr.modf() {
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return Err(Error::ModeFault);
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}
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if sr.crcerr() {
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return Err(Error::Crc);
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}
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if sr.txe() {
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unsafe {
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let dr = regs.dr().ptr() as *mut W;
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ptr::write_volatile(dr, word);
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}
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return Ok(());
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}
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}
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}
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/// Read a single word blocking. Assumes word size have already been set.
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fn read_word<W: Word>(regs: &'static crate::pac::spi::Spi) -> Result<W, Error> {
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loop {
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let sr = unsafe { regs.sr().read() };
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if sr.ovr() {
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return Err(Error::Overrun);
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}
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#[cfg(not(spi_f1))]
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if sr.fre() {
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return Err(Error::Framing);
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}
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if sr.modf() {
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return Err(Error::ModeFault);
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}
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if sr.crcerr() {
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return Err(Error::Crc);
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}
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if sr.rxne() {
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unsafe {
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let dr = regs.dr().ptr() as *const W;
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return Ok(ptr::read_volatile(dr));
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}
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}
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}
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}
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