564 lines
18 KiB
Rust
564 lines
18 KiB
Rust
#![macro_use]
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use core::future::poll_fn;
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use core::sync::atomic::{compiler_fence, Ordering};
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use core::task::Poll;
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use embassy_embedded_hal::SetConfig;
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use embassy_hal_common::{into_ref, PeripheralRef};
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pub use embedded_hal_02::spi::{Mode, Phase, Polarity, MODE_0, MODE_1, MODE_2, MODE_3};
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pub use pac::spim0::frequency::FREQUENCY_A as Frequency;
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use crate::chip::FORCE_COPY_BUFFER_SIZE;
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use crate::gpio::sealed::Pin as _;
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use crate::gpio::{self, AnyPin, Pin as GpioPin, PselBits};
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use crate::interrupt::{Interrupt, InterruptExt};
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use crate::util::{slice_in_ram_or, slice_ptr_parts, slice_ptr_parts_mut};
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use crate::{pac, Peripheral};
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#[derive(Debug, Clone, Copy, PartialEq, Eq)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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#[non_exhaustive]
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pub enum Error {
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TxBufferTooLong,
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RxBufferTooLong,
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/// EasyDMA can only read from data memory, read only buffers in flash will fail.
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DMABufferNotInDataMemory,
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}
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/// Interface for the SPIM peripheral using EasyDMA to offload the transmission and reception workload.
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///
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/// For more details about EasyDMA, consult the module documentation.
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pub struct Spim<'d, T: Instance> {
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_p: PeripheralRef<'d, T>,
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}
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#[non_exhaustive]
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pub struct Config {
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pub frequency: Frequency,
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pub mode: Mode,
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pub orc: u8,
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}
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impl Default for Config {
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fn default() -> Self {
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Self {
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frequency: Frequency::M1,
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mode: MODE_0,
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orc: 0x00,
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}
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}
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}
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impl<'d, T: Instance> Spim<'d, T> {
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pub fn new(
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spim: impl Peripheral<P = T> + 'd,
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irq: impl Peripheral<P = T::Interrupt> + 'd,
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sck: impl Peripheral<P = impl GpioPin> + 'd,
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miso: impl Peripheral<P = impl GpioPin> + 'd,
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mosi: impl Peripheral<P = impl GpioPin> + 'd,
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config: Config,
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) -> Self {
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into_ref!(sck, miso, mosi);
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Self::new_inner(
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spim,
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irq,
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sck.map_into(),
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Some(miso.map_into()),
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Some(mosi.map_into()),
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config,
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)
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}
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pub fn new_txonly(
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spim: impl Peripheral<P = T> + 'd,
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irq: impl Peripheral<P = T::Interrupt> + 'd,
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sck: impl Peripheral<P = impl GpioPin> + 'd,
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mosi: impl Peripheral<P = impl GpioPin> + 'd,
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config: Config,
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) -> Self {
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into_ref!(sck, mosi);
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Self::new_inner(spim, irq, sck.map_into(), None, Some(mosi.map_into()), config)
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}
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pub fn new_rxonly(
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spim: impl Peripheral<P = T> + 'd,
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irq: impl Peripheral<P = T::Interrupt> + 'd,
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sck: impl Peripheral<P = impl GpioPin> + 'd,
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miso: impl Peripheral<P = impl GpioPin> + 'd,
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config: Config,
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) -> Self {
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into_ref!(sck, miso);
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Self::new_inner(spim, irq, sck.map_into(), Some(miso.map_into()), None, config)
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}
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fn new_inner(
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spim: impl Peripheral<P = T> + 'd,
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irq: impl Peripheral<P = T::Interrupt> + 'd,
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sck: PeripheralRef<'d, AnyPin>,
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miso: Option<PeripheralRef<'d, AnyPin>>,
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mosi: Option<PeripheralRef<'d, AnyPin>>,
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config: Config,
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) -> Self {
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into_ref!(spim, irq);
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let r = T::regs();
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// Configure pins
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sck.conf().write(|w| w.dir().output().drive().h0h1());
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if let Some(mosi) = &mosi {
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mosi.conf().write(|w| w.dir().output().drive().h0h1());
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}
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if let Some(miso) = &miso {
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miso.conf().write(|w| w.input().connect().drive().h0h1());
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}
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match config.mode.polarity {
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Polarity::IdleHigh => {
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sck.set_high();
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if let Some(mosi) = &mosi {
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mosi.set_high();
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}
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}
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Polarity::IdleLow => {
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sck.set_low();
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if let Some(mosi) = &mosi {
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mosi.set_low();
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}
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}
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}
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// Select pins.
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r.psel.sck.write(|w| unsafe { w.bits(sck.psel_bits()) });
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r.psel.mosi.write(|w| unsafe { w.bits(mosi.psel_bits()) });
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r.psel.miso.write(|w| unsafe { w.bits(miso.psel_bits()) });
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// Enable SPIM instance.
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r.enable.write(|w| w.enable().enabled());
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// Configure mode.
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let mode = config.mode;
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r.config.write(|w| {
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match mode {
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MODE_0 => {
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w.order().msb_first();
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w.cpol().active_high();
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w.cpha().leading();
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}
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MODE_1 => {
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w.order().msb_first();
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w.cpol().active_high();
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w.cpha().trailing();
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}
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MODE_2 => {
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w.order().msb_first();
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w.cpol().active_low();
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w.cpha().leading();
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}
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MODE_3 => {
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w.order().msb_first();
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w.cpol().active_low();
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w.cpha().trailing();
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}
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}
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w
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});
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// Configure frequency.
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let frequency = config.frequency;
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r.frequency.write(|w| w.frequency().variant(frequency));
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// Set over-read character
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let orc = config.orc;
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r.orc.write(|w| unsafe { w.orc().bits(orc) });
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// Disable all events interrupts
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r.intenclr.write(|w| unsafe { w.bits(0xFFFF_FFFF) });
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irq.set_handler(Self::on_interrupt);
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irq.unpend();
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irq.enable();
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Self { _p: spim }
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}
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fn on_interrupt(_: *mut ()) {
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let r = T::regs();
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let s = T::state();
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if r.events_end.read().bits() != 0 {
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s.end_waker.wake();
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r.intenclr.write(|w| w.end().clear());
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}
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}
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fn prepare(&mut self, rx: *mut [u8], tx: *const [u8]) -> Result<(), Error> {
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slice_in_ram_or(tx, Error::DMABufferNotInDataMemory)?;
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// NOTE: RAM slice check for rx is not necessary, as a mutable
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// slice can only be built from data located in RAM.
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compiler_fence(Ordering::SeqCst);
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let r = T::regs();
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// Set up the DMA write.
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let (ptr, len) = slice_ptr_parts(tx);
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r.txd.ptr.write(|w| unsafe { w.ptr().bits(ptr as _) });
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r.txd.maxcnt.write(|w| unsafe { w.maxcnt().bits(len as _) });
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// Set up the DMA read.
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let (ptr, len) = slice_ptr_parts_mut(rx);
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r.rxd.ptr.write(|w| unsafe { w.ptr().bits(ptr as _) });
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r.rxd.maxcnt.write(|w| unsafe { w.maxcnt().bits(len as _) });
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// Reset and enable the event
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r.events_end.reset();
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r.intenset.write(|w| w.end().set());
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// Start SPI transaction.
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r.tasks_start.write(|w| unsafe { w.bits(1) });
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Ok(())
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}
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fn blocking_inner_from_ram(&mut self, rx: *mut [u8], tx: *const [u8]) -> Result<(), Error> {
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self.prepare(rx, tx)?;
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// Wait for 'end' event.
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while T::regs().events_end.read().bits() == 0 {}
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compiler_fence(Ordering::SeqCst);
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Ok(())
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}
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fn blocking_inner(&mut self, rx: &mut [u8], tx: &[u8]) -> Result<(), Error> {
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match self.blocking_inner_from_ram(rx, tx) {
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Ok(_) => Ok(()),
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Err(Error::DMABufferNotInDataMemory) => {
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trace!("Copying SPIM tx buffer into RAM for DMA");
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let tx_ram_buf = &mut [0; FORCE_COPY_BUFFER_SIZE][..tx.len()];
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tx_ram_buf.copy_from_slice(tx);
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self.blocking_inner_from_ram(rx, tx_ram_buf)
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}
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Err(error) => Err(error),
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}
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}
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async fn async_inner_from_ram(&mut self, rx: *mut [u8], tx: *const [u8]) -> Result<(), Error> {
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self.prepare(rx, tx)?;
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// Wait for 'end' event.
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poll_fn(|cx| {
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T::state().end_waker.register(cx.waker());
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if T::regs().events_end.read().bits() != 0 {
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return Poll::Ready(());
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}
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Poll::Pending
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})
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.await;
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compiler_fence(Ordering::SeqCst);
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Ok(())
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}
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async fn async_inner(&mut self, rx: &mut [u8], tx: &[u8]) -> Result<(), Error> {
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match self.async_inner_from_ram(rx, tx).await {
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Ok(_) => Ok(()),
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Err(Error::DMABufferNotInDataMemory) => {
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trace!("Copying SPIM tx buffer into RAM for DMA");
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let tx_ram_buf = &mut [0; FORCE_COPY_BUFFER_SIZE][..tx.len()];
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tx_ram_buf.copy_from_slice(tx);
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self.async_inner_from_ram(rx, tx_ram_buf).await
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}
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Err(error) => Err(error),
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}
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}
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/// Reads data from the SPI bus without sending anything. Blocks until the buffer has been filled.
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pub fn blocking_read(&mut self, data: &mut [u8]) -> Result<(), Error> {
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self.blocking_inner(data, &[])
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}
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/// Simultaneously sends and receives data. Blocks until the transmission is completed.
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/// If necessary, the write buffer will be copied into RAM (see struct description for detail).
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pub fn blocking_transfer(&mut self, read: &mut [u8], write: &[u8]) -> Result<(), Error> {
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self.blocking_inner(read, write)
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}
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/// Same as [`blocking_transfer`](Spim::blocking_transfer) but will fail instead of copying data into RAM. Consult the module level documentation to learn more.
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pub fn blocking_transfer_from_ram(&mut self, read: &mut [u8], write: &[u8]) -> Result<(), Error> {
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self.blocking_inner(read, write)
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}
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/// Simultaneously sends and receives data.
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/// Places the received data into the same buffer and blocks until the transmission is completed.
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pub fn blocking_transfer_in_place(&mut self, data: &mut [u8]) -> Result<(), Error> {
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self.blocking_inner_from_ram(data, data)
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}
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/// Sends data, discarding any received data. Blocks until the transmission is completed.
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/// If necessary, the write buffer will be copied into RAM (see struct description for detail).
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pub fn blocking_write(&mut self, data: &[u8]) -> Result<(), Error> {
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self.blocking_inner(&mut [], data)
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}
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/// Same as [`blocking_write`](Spim::blocking_write) but will fail instead of copying data into RAM. Consult the module level documentation to learn more.
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pub fn blocking_write_from_ram(&mut self, data: &[u8]) -> Result<(), Error> {
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self.blocking_inner(&mut [], data)
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}
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/// Reads data from the SPI bus without sending anything.
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pub async fn read(&mut self, data: &mut [u8]) -> Result<(), Error> {
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self.async_inner(data, &[]).await
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}
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/// Simultaneously sends and receives data.
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/// If necessary, the write buffer will be copied into RAM (see struct description for detail).
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pub async fn transfer(&mut self, read: &mut [u8], write: &[u8]) -> Result<(), Error> {
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self.async_inner(read, write).await
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}
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/// Same as [`transfer`](Spim::transfer) but will fail instead of copying data into RAM. Consult the module level documentation to learn more.
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pub async fn transfer_from_ram(&mut self, read: &mut [u8], write: &[u8]) -> Result<(), Error> {
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self.async_inner_from_ram(read, write).await
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}
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/// Simultaneously sends and receives data. Places the received data into the same buffer.
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pub async fn transfer_in_place(&mut self, data: &mut [u8]) -> Result<(), Error> {
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self.async_inner_from_ram(data, data).await
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}
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/// Sends data, discarding any received data.
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/// If necessary, the write buffer will be copied into RAM (see struct description for detail).
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pub async fn write(&mut self, data: &[u8]) -> Result<(), Error> {
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self.async_inner(&mut [], data).await
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}
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/// Same as [`write`](Spim::write) but will fail instead of copying data into RAM. Consult the module level documentation to learn more.
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pub async fn write_from_ram(&mut self, data: &[u8]) -> Result<(), Error> {
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self.async_inner_from_ram(&mut [], data).await
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}
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}
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impl<'d, T: Instance> Drop for Spim<'d, T> {
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fn drop(&mut self) {
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trace!("spim drop");
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// TODO check for abort, wait for xxxstopped
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// disable!
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let r = T::regs();
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r.enable.write(|w| w.enable().disabled());
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gpio::deconfigure_pin(r.psel.sck.read().bits());
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gpio::deconfigure_pin(r.psel.miso.read().bits());
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gpio::deconfigure_pin(r.psel.mosi.read().bits());
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trace!("spim drop: done");
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}
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}
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pub(crate) mod sealed {
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use embassy_sync::waitqueue::AtomicWaker;
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use super::*;
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pub struct State {
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pub end_waker: AtomicWaker,
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}
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impl State {
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pub const fn new() -> Self {
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Self {
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end_waker: AtomicWaker::new(),
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}
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}
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}
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pub trait Instance {
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fn regs() -> &'static pac::spim0::RegisterBlock;
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fn state() -> &'static State;
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}
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}
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pub trait Instance: Peripheral<P = Self> + sealed::Instance + 'static {
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type Interrupt: Interrupt;
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}
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macro_rules! impl_spim {
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($type:ident, $pac_type:ident, $irq:ident) => {
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impl crate::spim::sealed::Instance for peripherals::$type {
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fn regs() -> &'static pac::spim0::RegisterBlock {
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unsafe { &*pac::$pac_type::ptr() }
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}
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fn state() -> &'static crate::spim::sealed::State {
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static STATE: crate::spim::sealed::State = crate::spim::sealed::State::new();
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&STATE
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}
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}
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impl crate::spim::Instance for peripherals::$type {
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type Interrupt = crate::interrupt::$irq;
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}
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};
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}
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// ====================
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mod eh02 {
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use super::*;
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impl<'d, T: Instance> embedded_hal_02::blocking::spi::Transfer<u8> for Spim<'d, T> {
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type Error = Error;
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fn transfer<'w>(&mut self, words: &'w mut [u8]) -> Result<&'w [u8], Self::Error> {
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self.blocking_transfer_in_place(words)?;
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Ok(words)
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}
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}
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impl<'d, T: Instance> embedded_hal_02::blocking::spi::Write<u8> for Spim<'d, T> {
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type Error = Error;
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fn write(&mut self, words: &[u8]) -> Result<(), Self::Error> {
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self.blocking_write(words)
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}
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}
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}
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#[cfg(feature = "unstable-traits")]
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mod eh1 {
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use super::*;
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impl embedded_hal_1::spi::Error for Error {
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fn kind(&self) -> embedded_hal_1::spi::ErrorKind {
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match *self {
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Self::TxBufferTooLong => embedded_hal_1::spi::ErrorKind::Other,
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Self::RxBufferTooLong => embedded_hal_1::spi::ErrorKind::Other,
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Self::DMABufferNotInDataMemory => embedded_hal_1::spi::ErrorKind::Other,
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}
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}
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}
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impl<'d, T: Instance> embedded_hal_1::spi::ErrorType for Spim<'d, T> {
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type Error = Error;
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}
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impl<'d, T: Instance> embedded_hal_1::spi::SpiBusFlush for Spim<'d, T> {
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fn flush(&mut self) -> Result<(), Self::Error> {
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Ok(())
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}
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}
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impl<'d, T: Instance> embedded_hal_1::spi::SpiBusRead<u8> for Spim<'d, T> {
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fn read(&mut self, words: &mut [u8]) -> Result<(), Self::Error> {
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self.blocking_transfer(words, &[])
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}
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}
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impl<'d, T: Instance> embedded_hal_1::spi::SpiBusWrite<u8> for Spim<'d, T> {
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fn write(&mut self, words: &[u8]) -> Result<(), Self::Error> {
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self.blocking_write(words)
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}
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}
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impl<'d, T: Instance> embedded_hal_1::spi::SpiBus<u8> for Spim<'d, T> {
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fn transfer(&mut self, read: &mut [u8], write: &[u8]) -> Result<(), Self::Error> {
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self.blocking_transfer(read, write)
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}
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fn transfer_in_place(&mut self, words: &mut [u8]) -> Result<(), Self::Error> {
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self.blocking_transfer_in_place(words)
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}
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}
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}
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#[cfg(all(feature = "unstable-traits", feature = "nightly"))]
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mod eha {
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use core::future::Future;
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use super::*;
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impl<'d, T: Instance> embedded_hal_async::spi::SpiBusFlush for Spim<'d, T> {
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type FlushFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a;
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fn flush<'a>(&'a mut self) -> Self::FlushFuture<'a> {
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async move { Ok(()) }
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|
}
|
|
}
|
|
|
|
impl<'d, T: Instance> embedded_hal_async::spi::SpiBusRead<u8> for Spim<'d, T> {
|
|
type ReadFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a;
|
|
|
|
fn read<'a>(&'a mut self, words: &'a mut [u8]) -> Self::ReadFuture<'a> {
|
|
self.read(words)
|
|
}
|
|
}
|
|
|
|
impl<'d, T: Instance> embedded_hal_async::spi::SpiBusWrite<u8> for Spim<'d, T> {
|
|
type WriteFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a;
|
|
|
|
fn write<'a>(&'a mut self, data: &'a [u8]) -> Self::WriteFuture<'a> {
|
|
self.write(data)
|
|
}
|
|
}
|
|
|
|
impl<'d, T: Instance> embedded_hal_async::spi::SpiBus<u8> for Spim<'d, T> {
|
|
type TransferFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a;
|
|
|
|
fn transfer<'a>(&'a mut self, rx: &'a mut [u8], tx: &'a [u8]) -> Self::TransferFuture<'a> {
|
|
self.transfer(rx, tx)
|
|
}
|
|
|
|
type TransferInPlaceFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a;
|
|
|
|
fn transfer_in_place<'a>(&'a mut self, words: &'a mut [u8]) -> Self::TransferInPlaceFuture<'a> {
|
|
self.transfer_in_place(words)
|
|
}
|
|
}
|
|
}
|
|
|
|
impl<'d, T: Instance> SetConfig for Spim<'d, T> {
|
|
type Config = Config;
|
|
fn set_config(&mut self, config: &Self::Config) {
|
|
let r = T::regs();
|
|
// Configure mode.
|
|
let mode = config.mode;
|
|
r.config.write(|w| {
|
|
match mode {
|
|
MODE_0 => {
|
|
w.order().msb_first();
|
|
w.cpol().active_high();
|
|
w.cpha().leading();
|
|
}
|
|
MODE_1 => {
|
|
w.order().msb_first();
|
|
w.cpol().active_high();
|
|
w.cpha().trailing();
|
|
}
|
|
MODE_2 => {
|
|
w.order().msb_first();
|
|
w.cpol().active_low();
|
|
w.cpha().leading();
|
|
}
|
|
MODE_3 => {
|
|
w.order().msb_first();
|
|
w.cpol().active_low();
|
|
w.cpha().trailing();
|
|
}
|
|
}
|
|
|
|
w
|
|
});
|
|
|
|
// Configure frequency.
|
|
let frequency = config.frequency;
|
|
r.frequency.write(|w| w.frequency().variant(frequency));
|
|
|
|
// Set over-read character
|
|
let orc = config.orc;
|
|
r.orc.write(|w| unsafe { w.orc().bits(orc) });
|
|
}
|
|
}
|