103 lines
2.8 KiB
Rust
103 lines
2.8 KiB
Rust
use crate::device::RegisterBlock;
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use crate::spi::SpiInterface;
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use embedded_hal_async::spi::SpiDevice;
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pub const MODE: u16 = 0x00;
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pub const COMMAND: u16 = 0x01;
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pub const RXBUF_SIZE: u16 = 0x1E;
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pub const TXBUF_SIZE: u16 = 0x1F;
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pub const TX_FREE_SIZE: u16 = 0x20;
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pub const TX_DATA_WRITE_PTR: u16 = 0x24;
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pub const RECVD_SIZE: u16 = 0x26;
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pub const RX_DATA_READ_PTR: u16 = 0x28;
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pub const SOCKET_INTR_MASK: u16 = 0x2C;
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#[repr(u8)]
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pub enum Command {
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Open = 0x01,
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Send = 0x20,
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Receive = 0x40,
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}
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pub const INTR: u16 = 0x02;
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#[repr(u8)]
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pub enum Interrupt {
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Receive = 0b00100_u8,
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}
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pub async fn reset_interrupt<SPI: SpiDevice>(
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bus: &mut SpiInterface<SPI>,
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code: Interrupt,
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) -> Result<(), SPI::Error> {
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let data = [code as u8];
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bus.write_frame(RegisterBlock::Socket0, INTR, &data).await
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}
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pub async fn get_tx_write_ptr<SPI: SpiDevice>(
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bus: &mut SpiInterface<SPI>,
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) -> Result<u16, SPI::Error> {
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let mut data = [0u8; 2];
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bus.read_frame(RegisterBlock::Socket0, TX_DATA_WRITE_PTR, &mut data)
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.await?;
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Ok(u16::from_be_bytes(data))
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}
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pub async fn set_tx_write_ptr<SPI: SpiDevice>(
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bus: &mut SpiInterface<SPI>,
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ptr: u16,
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) -> Result<(), SPI::Error> {
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let data = ptr.to_be_bytes();
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bus.write_frame(RegisterBlock::Socket0, TX_DATA_WRITE_PTR, &data)
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.await
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}
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pub async fn get_rx_read_ptr<SPI: SpiDevice>(
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bus: &mut SpiInterface<SPI>,
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) -> Result<u16, SPI::Error> {
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let mut data = [0u8; 2];
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bus.read_frame(RegisterBlock::Socket0, RX_DATA_READ_PTR, &mut data)
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.await?;
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Ok(u16::from_be_bytes(data))
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}
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pub async fn set_rx_read_ptr<SPI: SpiDevice>(
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bus: &mut SpiInterface<SPI>,
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ptr: u16,
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) -> Result<(), SPI::Error> {
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let data = ptr.to_be_bytes();
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bus.write_frame(RegisterBlock::Socket0, RX_DATA_READ_PTR, &data)
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.await
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}
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pub async fn command<SPI: SpiDevice>(
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bus: &mut SpiInterface<SPI>,
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command: Command,
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) -> Result<(), SPI::Error> {
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let data = [command as u8];
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bus.write_frame(RegisterBlock::Socket0, COMMAND, &data)
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.await
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}
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pub async fn get_rx_size<SPI: SpiDevice>(bus: &mut SpiInterface<SPI>) -> Result<u16, SPI::Error> {
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loop {
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// Wait until two sequential reads are equal
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let mut res0 = [0u8; 2];
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bus.read_frame(RegisterBlock::Socket0, RECVD_SIZE, &mut res0)
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.await?;
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let mut res1 = [0u8; 2];
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bus.read_frame(RegisterBlock::Socket0, RECVD_SIZE, &mut res1)
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.await?;
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if res0 == res1 {
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break Ok(u16::from_be_bytes(res0));
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}
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}
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}
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pub async fn get_tx_free_size<SPI: SpiDevice>(
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bus: &mut SpiInterface<SPI>,
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) -> Result<u16, SPI::Error> {
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let mut data = [0; 2];
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bus.read_frame(RegisterBlock::Socket0, TX_FREE_SIZE, &mut data)
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.await?;
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Ok(u16::from_be_bytes(data))
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}
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