408 lines
12 KiB
Rust
408 lines
12 KiB
Rust
use crate::pac::rcc::regs::Cfgr;
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use crate::pac::rcc::vals::Msirgsel;
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pub use crate::pac::rcc::vals::{
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Clk48sel as Clk48Src, Hpre as AHBPrescaler, Msirange as MSIRange, Pllm as PllPreDiv, Plln as PllMul,
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Pllp as PllPDiv, Pllq as PllQDiv, Pllr as PllRDiv, Pllsrc as PLLSource, Ppre as APBPrescaler, Sw as ClockSrc,
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};
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use crate::pac::{FLASH, RCC};
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use crate::rcc::{set_freqs, Clocks};
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use crate::time::Hertz;
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/// HSI speed
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pub const HSI_FREQ: Hertz = Hertz(16_000_000);
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#[derive(Clone, Copy)]
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pub struct Pll {
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/// PLL source
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pub source: PLLSource,
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/// PLL pre-divider (DIVM).
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pub prediv: PllPreDiv,
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/// PLL multiplication factor.
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pub mul: PllMul,
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/// PLL P division factor. If None, PLL P output is disabled.
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pub divp: Option<PllPDiv>,
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/// PLL Q division factor. If None, PLL Q output is disabled.
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pub divq: Option<PllQDiv>,
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/// PLL R division factor. If None, PLL R output is disabled.
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pub divr: Option<PllRDiv>,
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}
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/// Clocks configutation
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pub struct Config {
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// base clock sources
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pub msi: Option<MSIRange>,
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pub hsi16: bool,
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pub hse: Option<Hertz>,
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#[cfg(not(any(stm32l47x, stm32l48x)))]
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pub hsi48: bool,
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// pll
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pub pll: Option<Pll>,
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pub pllsai1: Option<Pll>,
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#[cfg(any(
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stm32l47x, stm32l48x, stm32l49x, stm32l4ax, stm32l4px, stm32l4qx, stm32l4rx, stm32l4sx
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))]
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pub pllsai2: Option<Pll>,
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// sysclk, buses.
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pub mux: ClockSrc,
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pub ahb_pre: AHBPrescaler,
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pub apb1_pre: APBPrescaler,
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pub apb2_pre: APBPrescaler,
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// muxes
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pub clk48_src: Clk48Src,
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// low speed LSI/LSE/RTC
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pub ls: super::LsConfig,
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}
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impl Default for Config {
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#[inline]
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fn default() -> Config {
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Config {
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hse: None,
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hsi16: false,
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msi: Some(MSIRange::RANGE4M),
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mux: ClockSrc::MSI,
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ahb_pre: AHBPrescaler::DIV1,
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apb1_pre: APBPrescaler::DIV1,
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apb2_pre: APBPrescaler::DIV1,
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pll: None,
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pllsai1: None,
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#[cfg(any(
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stm32l47x, stm32l48x, stm32l49x, stm32l4ax, stm32l4px, stm32l4qx, stm32l4rx, stm32l4sx
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))]
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pllsai2: None,
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#[cfg(not(any(stm32l471, stm32l475, stm32l476, stm32l486)))]
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hsi48: true,
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clk48_src: Clk48Src::HSI48,
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ls: Default::default(),
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}
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}
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}
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pub(crate) unsafe fn init(config: Config) {
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// Switch to MSI to prevent problems with PLL configuration.
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if !RCC.cr().read().msion() {
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// Turn on MSI and configure it to 4MHz.
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RCC.cr().modify(|w| {
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w.set_msirgsel(Msirgsel::CR);
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w.set_msirange(MSIRange::RANGE4M);
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w.set_msipllen(false);
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w.set_msion(true)
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});
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// Wait until MSI is running
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while !RCC.cr().read().msirdy() {}
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}
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if RCC.cfgr().read().sws() != ClockSrc::MSI {
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// Set MSI as a clock source, reset prescalers.
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RCC.cfgr().write_value(Cfgr::default());
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// Wait for clock switch status bits to change.
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while RCC.cfgr().read().sws() != ClockSrc::MSI {}
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}
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let rtc = config.ls.init();
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let msi = config.msi.map(|range| {
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// Enable MSI
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RCC.cr().write(|w| {
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w.set_msirange(range);
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w.set_msirgsel(Msirgsel::CR);
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w.set_msion(true);
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// If LSE is enabled, enable calibration of MSI
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w.set_msipllen(config.ls.lse.is_some());
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});
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while !RCC.cr().read().msirdy() {}
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// Enable as clock source for USB, RNG if running at 48 MHz
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if range == MSIRange::RANGE48M {}
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msirange_to_hertz(range)
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});
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let hsi16 = config.hsi16.then(|| {
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RCC.cr().write(|w| w.set_hsion(true));
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while !RCC.cr().read().hsirdy() {}
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HSI_FREQ
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});
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let hse = config.hse.map(|freq| {
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RCC.cr().write(|w| w.set_hseon(true));
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while !RCC.cr().read().hserdy() {}
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freq
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});
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#[cfg(not(any(stm32l47x, stm32l48x)))]
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let hsi48 = config.hsi48.then(|| {
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RCC.crrcr().modify(|w| w.set_hsi48on(true));
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while !RCC.crrcr().read().hsi48rdy() {}
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Hertz(48_000_000)
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});
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#[cfg(any(stm32l47x, stm32l48x))]
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let hsi48 = None;
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let _plls = [
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&config.pll,
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&config.pllsai1,
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#[cfg(any(
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stm32l47x, stm32l48x, stm32l49x, stm32l4ax, stm32l4px, stm32l4qx, stm32l4rx, stm32l4sx
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))]
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&config.pllsai2,
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];
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// L4 has shared PLLSRC, PLLM, check it's equal in all PLLs.
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#[cfg(all(stm32l4, not(any(stm32l4px, stm32l4qx, stm32l4rx, stm32l4sx))))]
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match get_equal(_plls.into_iter().flatten().map(|p| (p.source, p.prediv))) {
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Err(()) => panic!("Source must be equal across all enabled PLLs."),
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Ok(None) => {}
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Ok(Some((source, prediv))) => RCC.pllcfgr().write(|w| {
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w.set_pllm(prediv);
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w.set_pllsrc(source);
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}),
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};
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// L4+ has shared PLLSRC, check it's equal in all PLLs.
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#[cfg(any(stm32l4px, stm32l4qx, stm32l4rx, stm32l4sx))]
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match get_equal(_plls.into_iter().flatten().map(|p| p.source)) {
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Err(()) => panic!("Source must be equal across all enabled PLLs."),
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Ok(None) => {}
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Ok(Some(source)) => RCC.pllcfgr().write(|w| {
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w.set_pllsrc(source);
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}),
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};
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let pll_input = PllInput { hse, hsi16, msi };
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let pll = init_pll(PllInstance::Pll, config.pll, &pll_input);
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let pllsai1 = init_pll(PllInstance::Pllsai1, config.pllsai1, &pll_input);
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#[cfg(any(
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stm32l47x, stm32l48x, stm32l49x, stm32l4ax, stm32l4px, stm32l4qx, stm32l4rx, stm32l4sx
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))]
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let _pllsai2 = init_pll(PllInstance::Pllsai2, config.pllsai2, &pll_input);
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let sys_clk = match config.mux {
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ClockSrc::HSE => hse.unwrap(),
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ClockSrc::HSI16 => hsi16.unwrap(),
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ClockSrc::MSI => msi.unwrap(),
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ClockSrc::PLL => pll._r.unwrap(),
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};
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let _clk48 = match config.clk48_src {
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Clk48Src::HSI48 => hsi48,
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Clk48Src::MSI => msi,
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Clk48Src::PLLSAI1_Q => pllsai1._q,
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Clk48Src::PLL_Q => pll._q,
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};
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#[cfg(any(stm32l4px, stm32l4qx, stm32l4rx, stm32l4sx))]
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assert!(sys_clk.0 <= 120_000_000);
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#[cfg(not(any(stm32l4px, stm32l4qx, stm32l4rx, stm32l4sx)))]
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assert!(sys_clk.0 <= 80_000_000);
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// Set flash wait states
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FLASH.acr().modify(|w| {
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w.set_latency(match sys_clk.0 {
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0..=16_000_000 => 0,
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0..=32_000_000 => 1,
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0..=48_000_000 => 2,
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0..=64_000_000 => 3,
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_ => 4,
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})
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});
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RCC.cfgr().modify(|w| {
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w.set_sw(config.mux);
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w.set_hpre(config.ahb_pre);
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w.set_ppre1(config.apb1_pre);
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w.set_ppre2(config.apb2_pre);
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});
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let ahb_freq = sys_clk / config.ahb_pre;
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let (apb1_freq, apb1_tim_freq) = match config.apb1_pre {
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APBPrescaler::DIV1 => (ahb_freq, ahb_freq),
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pre => {
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let freq = ahb_freq / pre;
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(freq, freq * 2u32)
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}
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};
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let (apb2_freq, apb2_tim_freq) = match config.apb2_pre {
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APBPrescaler::DIV1 => (ahb_freq, ahb_freq),
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pre => {
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let freq = ahb_freq / pre;
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(freq, freq * 2u32)
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}
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};
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set_freqs(Clocks {
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sys: sys_clk,
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hclk1: ahb_freq,
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hclk2: ahb_freq,
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hclk3: ahb_freq,
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pclk1: apb1_freq,
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pclk2: apb2_freq,
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pclk1_tim: apb1_tim_freq,
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pclk2_tim: apb2_tim_freq,
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rtc,
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});
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}
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fn msirange_to_hertz(range: MSIRange) -> Hertz {
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match range {
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MSIRange::RANGE100K => Hertz(100_000),
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MSIRange::RANGE200K => Hertz(200_000),
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MSIRange::RANGE400K => Hertz(400_000),
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MSIRange::RANGE800K => Hertz(800_000),
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MSIRange::RANGE1M => Hertz(1_000_000),
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MSIRange::RANGE2M => Hertz(2_000_000),
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MSIRange::RANGE4M => Hertz(4_000_000),
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MSIRange::RANGE8M => Hertz(8_000_000),
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MSIRange::RANGE16M => Hertz(16_000_000),
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MSIRange::RANGE24M => Hertz(24_000_000),
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MSIRange::RANGE32M => Hertz(32_000_000),
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MSIRange::RANGE48M => Hertz(48_000_000),
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_ => unreachable!(),
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}
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}
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fn get_equal<T: Eq>(mut iter: impl Iterator<Item = T>) -> Result<Option<T>, ()> {
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let Some(x) = iter.next() else { return Ok(None) };
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if !iter.all(|y| y == x) {
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return Err(());
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}
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return Ok(Some(x));
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}
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struct PllInput {
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hsi16: Option<Hertz>,
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hse: Option<Hertz>,
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msi: Option<Hertz>,
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}
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#[derive(Default)]
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struct PllOutput {
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_p: Option<Hertz>,
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_q: Option<Hertz>,
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_r: Option<Hertz>,
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}
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#[derive(PartialEq, Eq, Clone, Copy)]
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enum PllInstance {
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Pll,
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Pllsai1,
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#[cfg(any(
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stm32l47x, stm32l48x, stm32l49x, stm32l4ax, stm32l4px, stm32l4qx, stm32l4rx, stm32l4sx
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))]
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Pllsai2,
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}
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fn init_pll(instance: PllInstance, config: Option<Pll>, input: &PllInput) -> PllOutput {
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// Disable PLL
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match instance {
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PllInstance::Pll => {
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RCC.cr().modify(|w| w.set_pllon(false));
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while RCC.cr().read().pllrdy() {}
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}
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PllInstance::Pllsai1 => {
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RCC.cr().modify(|w| w.set_pllsai1on(false));
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while RCC.cr().read().pllsai1rdy() {}
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}
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#[cfg(any(
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stm32l47x, stm32l48x, stm32l49x, stm32l4ax, stm32l4px, stm32l4qx, stm32l4rx, stm32l4sx
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))]
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PllInstance::Pllsai2 => {
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RCC.cr().modify(|w| w.set_pllsai2on(false));
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while RCC.cr().read().pllsai2rdy() {}
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}
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}
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let Some(pll) = config else { return PllOutput::default() };
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let pll_src = match pll.source {
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PLLSource::NONE => panic!("must not select PLL source as NONE"),
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PLLSource::HSE => input.hse,
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PLLSource::HSI16 => input.hsi16,
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PLLSource::MSI => input.msi,
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};
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let pll_src = pll_src.unwrap();
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let vco_freq = pll_src / pll.prediv * pll.mul;
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let p = pll.divp.map(|div| vco_freq / div);
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let q = pll.divq.map(|div| vco_freq / div);
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let r = pll.divr.map(|div| vco_freq / div);
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macro_rules! write_fields {
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($w:ident) => {
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$w.set_plln(pll.mul);
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if let Some(divp) = pll.divp {
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$w.set_pllp(divp);
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$w.set_pllpen(true);
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}
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if let Some(divq) = pll.divq {
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$w.set_pllq(divq);
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$w.set_pllqen(true);
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}
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if let Some(divr) = pll.divr {
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$w.set_pllr(divr);
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$w.set_pllren(true);
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}
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};
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}
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match instance {
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PllInstance::Pll => RCC.pllcfgr().write(|w| {
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w.set_pllm(pll.prediv);
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w.set_pllsrc(pll.source);
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write_fields!(w);
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}),
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PllInstance::Pllsai1 => RCC.pllsai1cfgr().write(|w| {
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#[cfg(any(stm32l4px, stm32l4qx, stm32l4rx, stm32l4sx, stm32l5))]
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w.set_pllm(pll.prediv);
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#[cfg(stm32l5)]
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w.set_pllsrc(pll.source);
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write_fields!(w);
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}),
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#[cfg(any(
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stm32l47x, stm32l48x, stm32l49x, stm32l4ax, stm32l4px, stm32l4qx, stm32l4rx, stm32l4sx
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))]
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PllInstance::Pllsai2 => RCC.pllsai2cfgr().write(|w| {
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#[cfg(any(stm32l4px, stm32l4qx, stm32l4rx, stm32l4sx, stm32l5))]
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w.set_pllm(pll.prediv);
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#[cfg(stm32l5)]
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w.set_pllsrc(pll.source);
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write_fields!(w);
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}),
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}
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// Enable PLL
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match instance {
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PllInstance::Pll => {
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RCC.cr().modify(|w| w.set_pllon(true));
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while !RCC.cr().read().pllrdy() {}
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}
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PllInstance::Pllsai1 => {
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RCC.cr().modify(|w| w.set_pllsai1on(true));
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while !RCC.cr().read().pllsai1rdy() {}
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}
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#[cfg(any(
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stm32l47x, stm32l48x, stm32l49x, stm32l4ax, stm32l4px, stm32l4qx, stm32l4rx, stm32l4sx
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))]
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PllInstance::Pllsai2 => {
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RCC.cr().modify(|w| w.set_pllsai2on(true));
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while !RCC.cr().read().pllsai2rdy() {}
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}
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}
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PllOutput { _p: p, _q: q, _r: r }
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}
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