6d0e6d563d
714: add more clock options for l4 and l5 r=Dirbaio a=ant32 - added an assert so it panics if pll48div is not 48Mhz - added MSI as a clock source for PLL - removed hsi48 option for MCUs mentioned in l4 rcc presentation - copied some code from l4 to l5, but don't have a way of testing it. Co-authored-by: Philip A Reimer <antreimer@gmail.com> |
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| src | ||
| build.rs | ||
| Cargo.toml | ||