257 lines
7.4 KiB
Rust
257 lines
7.4 KiB
Rust
use crate::pac::flash::vals::Latency;
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use crate::pac::rcc::vals::Pllsrc;
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#[cfg(any(rcc_f1, rcc_f1cl))]
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use crate::pac::rcc::vals::Usbpre;
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pub use crate::pac::rcc::vals::{
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Adcpre as ADCPrescaler, Hpre as AHBPrescaler, Pllmul as PllMul, Pllxtpre as PllPreDiv, Ppre as APBPrescaler,
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Sw as Sysclk,
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};
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use crate::pac::{FLASH, RCC};
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use crate::time::Hertz;
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/// HSI speed
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pub const HSI_FREQ: Hertz = Hertz(8_000_000);
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#[derive(Clone, Copy, Eq, PartialEq)]
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pub enum HseMode {
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/// crystal/ceramic oscillator (HSEBYP=0)
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Oscillator,
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/// external analog clock (low swing) (HSEBYP=1)
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Bypass,
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}
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#[derive(Clone, Copy, Eq, PartialEq)]
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pub struct Hse {
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/// HSE frequency.
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pub freq: Hertz,
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/// HSE mode.
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pub mode: HseMode,
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}
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#[derive(Clone, Copy, Eq, PartialEq)]
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pub enum PllSource {
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HSE,
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HSI,
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}
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#[derive(Clone, Copy)]
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pub struct Pll {
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pub src: PllSource,
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/// PLL pre-divider.
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///
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/// On some F3 chips, this must be 2 if `src == HSI`. Init will panic if this is not the case.
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pub prediv: PllPreDiv,
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/// PLL multiplication factor.
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pub mul: PllMul,
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}
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/// Clocks configutation
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#[non_exhaustive]
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pub struct Config {
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pub hsi: bool,
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pub hse: Option<Hse>,
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pub sys: Sysclk,
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pub pll: Option<Pll>,
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pub ahb_pre: AHBPrescaler,
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pub apb1_pre: APBPrescaler,
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pub apb2_pre: APBPrescaler,
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pub adc_pre: ADCPrescaler,
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pub ls: super::LsConfig,
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}
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impl Default for Config {
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fn default() -> Self {
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Self {
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hsi: true,
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hse: None,
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sys: Sysclk::HSI,
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pll: None,
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ahb_pre: AHBPrescaler::DIV1,
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apb1_pre: APBPrescaler::DIV1,
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apb2_pre: APBPrescaler::DIV1,
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ls: Default::default(),
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// ensure ADC is not out of range by default even if APB2 is maxxed out (36mhz)
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adc_pre: ADCPrescaler::DIV6,
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}
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}
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}
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/// Initialize and Set the clock frequencies
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pub(crate) unsafe fn init(config: Config) {
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// Configure HSI
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let hsi = match config.hsi {
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false => {
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RCC.cr().modify(|w| w.set_hsion(false));
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None
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}
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true => {
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RCC.cr().modify(|w| w.set_hsion(true));
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while !RCC.cr().read().hsirdy() {}
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Some(HSI_FREQ)
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}
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};
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// Configure HSE
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let hse = match config.hse {
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None => {
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RCC.cr().modify(|w| w.set_hseon(false));
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None
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}
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Some(hse) => {
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match hse.mode {
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HseMode::Bypass => assert!(max::HSE_BYP.contains(&hse.freq)),
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HseMode::Oscillator => assert!(max::HSE_OSC.contains(&hse.freq)),
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}
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RCC.cr().modify(|w| w.set_hsebyp(hse.mode != HseMode::Oscillator));
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RCC.cr().modify(|w| w.set_hseon(true));
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while !RCC.cr().read().hserdy() {}
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Some(hse.freq)
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}
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};
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// Enable PLL
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let pll = config.pll.map(|pll| {
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let (src_val, src_freq) = match pll.src {
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PllSource::HSI => {
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if pll.prediv != PllPreDiv::DIV2 {
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panic!("if PLL source is HSI, PLL prediv must be 2.");
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}
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(Pllsrc::HSI_DIV2, unwrap!(hsi))
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}
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PllSource::HSE => (Pllsrc::HSE_DIV_PREDIV, unwrap!(hse)),
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};
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let in_freq = src_freq / pll.prediv;
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assert!(max::PLL_IN.contains(&in_freq));
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let out_freq = in_freq * pll.mul;
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assert!(max::PLL_OUT.contains(&out_freq));
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RCC.cfgr().modify(|w| {
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w.set_pllmul(pll.mul);
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w.set_pllsrc(src_val);
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w.set_pllxtpre(pll.prediv);
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});
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RCC.cr().modify(|w| w.set_pllon(true));
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while !RCC.cr().read().pllrdy() {}
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out_freq
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});
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#[cfg(any(rcc_f1, rcc_f1cl))]
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let usb = match pll {
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Some(Hertz(72_000_000)) => {
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RCC.cfgr().modify(|w| w.set_usbpre(Usbpre::DIV1_5));
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Some(Hertz(48_000_000))
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}
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Some(Hertz(48_000_000)) => {
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RCC.cfgr().modify(|w| w.set_usbpre(Usbpre::DIV1));
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Some(Hertz(48_000_000))
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}
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_ => None,
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};
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// Configure sysclk
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let sys = match config.sys {
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Sysclk::HSI => unwrap!(hsi),
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Sysclk::HSE => unwrap!(hse),
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Sysclk::PLL1_P => unwrap!(pll),
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_ => unreachable!(),
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};
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let hclk = sys / config.ahb_pre;
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let (pclk1, pclk1_tim) = super::util::calc_pclk(hclk, config.apb1_pre);
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let (pclk2, pclk2_tim) = super::util::calc_pclk(hclk, config.apb2_pre);
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assert!(max::HCLK.contains(&hclk));
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assert!(max::PCLK1.contains(&pclk1));
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assert!(max::PCLK2.contains(&pclk2));
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let adc = pclk2 / config.adc_pre;
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assert!(max::ADC.contains(&adc));
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// Set latency based on HCLK frquency
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let latency = match hclk.0 {
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..=24_000_000 => Latency::WS0,
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..=48_000_000 => Latency::WS1,
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_ => Latency::WS2,
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};
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FLASH.acr().modify(|w| {
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w.set_latency(latency);
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// RM0316: "The prefetch buffer must be kept on when using a prescaler
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// different from 1 on the AHB clock.", "Half-cycle access cannot be
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// used when there is a prescaler different from 1 on the AHB clock"
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if config.ahb_pre != AHBPrescaler::DIV1 {
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w.set_hlfcya(false);
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w.set_prftbe(true);
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}
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});
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// Set prescalers
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// CFGR has been written before (PLL, PLL48) don't overwrite these settings
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RCC.cfgr().modify(|w| {
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w.set_ppre1(config.apb1_pre);
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w.set_ppre2(config.apb2_pre);
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w.set_hpre(config.ahb_pre);
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w.set_adcpre(config.adc_pre);
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});
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// Wait for the new prescalers to kick in
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// "The clocks are divided with the new prescaler factor from
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// 1 to 16 AHB cycles after write"
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cortex_m::asm::delay(16);
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// CFGR has been written before (PLL, PLL48, clock divider) don't overwrite these settings
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RCC.cfgr().modify(|w| w.set_sw(config.sys));
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while RCC.cfgr().read().sws() != config.sys {}
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let rtc = config.ls.init();
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set_clocks!(
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hsi: hsi,
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hse: hse,
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pll1_p: pll,
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sys: Some(sys),
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pclk1: Some(pclk1),
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pclk2: Some(pclk2),
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pclk1_tim: Some(pclk1_tim),
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pclk2_tim: Some(pclk2_tim),
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hclk1: Some(hclk),
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adc: Some(adc),
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rtc: rtc,
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#[cfg(any(rcc_f1, rcc_f1cl))]
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usb: usb,
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lse: None,
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);
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}
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mod max {
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use core::ops::RangeInclusive;
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use crate::time::Hertz;
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#[cfg(not(rcc_f1cl))]
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pub(crate) const HSE_OSC: RangeInclusive<Hertz> = Hertz(4_000_000)..=Hertz(16_000_000);
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#[cfg(not(rcc_f1cl))]
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pub(crate) const HSE_BYP: RangeInclusive<Hertz> = Hertz(1_000_000)..=Hertz(25_000_000);
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#[cfg(rcc_f1cl)]
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pub(crate) const HSE_OSC: RangeInclusive<Hertz> = Hertz(3_000_000)..=Hertz(25_000_000);
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#[cfg(rcc_f1cl)]
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pub(crate) const HSE_BYP: RangeInclusive<Hertz> = Hertz(1_000_000)..=Hertz(50_000_000);
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pub(crate) const HCLK: RangeInclusive<Hertz> = Hertz(0)..=Hertz(72_000_000);
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pub(crate) const PCLK1: RangeInclusive<Hertz> = Hertz(0)..=Hertz(36_000_000);
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pub(crate) const PCLK2: RangeInclusive<Hertz> = Hertz(0)..=Hertz(72_000_000);
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pub(crate) const PLL_IN: RangeInclusive<Hertz> = Hertz(1_000_000)..=Hertz(25_000_000);
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pub(crate) const PLL_OUT: RangeInclusive<Hertz> = Hertz(16_000_000)..=Hertz(72_000_000);
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pub(crate) const ADC: RangeInclusive<Hertz> = Hertz(0)..=Hertz(14_000_000);
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}
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