453 lines
16 KiB
Rust
453 lines
16 KiB
Rust
//! Async buffered UART
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//!
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//! WARNING!!! The functionality provided here is intended to be used only
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//! in situations where hardware flow control are available i.e. CTS and RTS.
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//! This is a problem that should be addressed at a later stage and can be
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//! fully explained at https://github.com/embassy-rs/embassy/issues/536.
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//!
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//! Note that discarding a future from a read or write operation may lead to losing
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//! data. For example, when using `futures_util::future::select` and completion occurs
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//! on the "other" future, you should capture the incomplete future and continue to use
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//! it for the next read or write. This pattern is a consideration for all IO, and not
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//! just serial communications.
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//!
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//! Please also see [crate::uarte] to understand when [BufferedUarte] should be used.
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use core::cmp::min;
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use core::future::Future;
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use core::marker::PhantomData;
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use core::sync::atomic::{compiler_fence, Ordering};
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use core::task::Poll;
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use embassy::waitqueue::WakerRegistration;
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use embassy_cortex_m::peripheral::{PeripheralMutex, PeripheralState, StateStorage};
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use embassy_hal_common::ring_buffer::RingBuffer;
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use embassy_hal_common::{low_power_wait_until, unborrow};
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use futures::future::poll_fn;
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// Re-export SVD variants to allow user to directly set values
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pub use pac::uarte0::{baudrate::BAUDRATE_A as Baudrate, config::PARITY_A as Parity};
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use crate::gpio::Pin as GpioPin;
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use crate::interrupt::InterruptExt;
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use crate::ppi::{AnyConfigurableChannel, ConfigurableChannel, Event, Ppi, Task};
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use crate::timer::{Frequency, Instance as TimerInstance, Timer};
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use crate::uarte::{apply_workaround_for_enable_anomaly, Config, Instance as UarteInstance};
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use crate::{pac, Unborrow};
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#[derive(Copy, Clone, Debug, PartialEq)]
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enum RxState {
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Idle,
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Receiving,
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}
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#[derive(Copy, Clone, Debug, PartialEq)]
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enum TxState {
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Idle,
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Transmitting(usize),
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}
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pub struct State<'d, U: UarteInstance, T: TimerInstance>(StateStorage<StateInner<'d, U, T>>);
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impl<'d, U: UarteInstance, T: TimerInstance> State<'d, U, T> {
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pub fn new() -> Self {
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Self(StateStorage::new())
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}
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}
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struct StateInner<'d, U: UarteInstance, T: TimerInstance> {
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phantom: PhantomData<&'d mut U>,
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timer: Timer<'d, T>,
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_ppi_ch1: Ppi<'d, AnyConfigurableChannel, 1, 2>,
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_ppi_ch2: Ppi<'d, AnyConfigurableChannel, 1, 1>,
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rx: RingBuffer<'d>,
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rx_state: RxState,
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rx_waker: WakerRegistration,
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tx: RingBuffer<'d>,
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tx_state: TxState,
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tx_waker: WakerRegistration,
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}
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/// Interface to a UARTE instance
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pub struct BufferedUarte<'d, U: UarteInstance, T: TimerInstance> {
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inner: PeripheralMutex<'d, StateInner<'d, U, T>>,
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}
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impl<'d, U: UarteInstance, T: TimerInstance> Unpin for BufferedUarte<'d, U, T> {}
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impl<'d, U: UarteInstance, T: TimerInstance> BufferedUarte<'d, U, T> {
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pub fn new(
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state: &'d mut State<'d, U, T>,
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_uarte: impl Unborrow<Target = U> + 'd,
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timer: impl Unborrow<Target = T> + 'd,
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ppi_ch1: impl Unborrow<Target = impl ConfigurableChannel + 'd> + 'd,
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ppi_ch2: impl Unborrow<Target = impl ConfigurableChannel + 'd> + 'd,
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irq: impl Unborrow<Target = U::Interrupt> + 'd,
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rxd: impl Unborrow<Target = impl GpioPin> + 'd,
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txd: impl Unborrow<Target = impl GpioPin> + 'd,
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cts: impl Unborrow<Target = impl GpioPin> + 'd,
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rts: impl Unborrow<Target = impl GpioPin> + 'd,
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config: Config,
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rx_buffer: &'d mut [u8],
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tx_buffer: &'d mut [u8],
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) -> Self {
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unborrow!(ppi_ch1, ppi_ch2, irq, rxd, txd, cts, rts);
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let r = U::regs();
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let mut timer = Timer::new(timer);
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rxd.conf().write(|w| w.input().connect().drive().h0h1());
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r.psel.rxd.write(|w| unsafe { w.bits(rxd.psel_bits()) });
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txd.set_high();
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txd.conf().write(|w| w.dir().output().drive().h0h1());
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r.psel.txd.write(|w| unsafe { w.bits(txd.psel_bits()) });
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cts.conf().write(|w| w.input().connect().drive().h0h1());
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r.psel.cts.write(|w| unsafe { w.bits(cts.psel_bits()) });
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rts.set_high();
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rts.conf().write(|w| w.dir().output().drive().h0h1());
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r.psel.rts.write(|w| unsafe { w.bits(rts.psel_bits()) });
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r.baudrate.write(|w| w.baudrate().variant(config.baudrate));
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r.config.write(|w| w.parity().variant(config.parity));
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// Configure
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r.config.write(|w| {
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w.hwfc().bit(true);
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w.parity().variant(config.parity);
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w
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});
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r.baudrate.write(|w| w.baudrate().variant(config.baudrate));
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// Enable interrupts
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r.intenset.write(|w| w.endrx().set().endtx().set());
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// Disable the irq, let the Registration enable it when everything is set up.
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irq.disable();
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irq.pend();
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// Enable UARTE instance
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apply_workaround_for_enable_anomaly(&r);
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r.enable.write(|w| w.enable().enabled());
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// BAUDRATE register values are `baudrate * 2^32 / 16000000`
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// source: https://devzone.nordicsemi.com/f/nordic-q-a/391/uart-baudrate-register-values
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//
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// We want to stop RX if line is idle for 2 bytes worth of time
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// That is 20 bits (each byte is 1 start bit + 8 data bits + 1 stop bit)
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// This gives us the amount of 16M ticks for 20 bits.
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let timeout = 0x8000_0000 / (config.baudrate as u32 / 40);
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timer.set_frequency(Frequency::F16MHz);
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timer.cc(0).write(timeout);
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timer.cc(0).short_compare_clear();
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timer.cc(0).short_compare_stop();
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let mut ppi_ch1 = Ppi::new_one_to_two(
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ppi_ch1.degrade(),
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Event::from_reg(&r.events_rxdrdy),
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timer.task_clear(),
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timer.task_start(),
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);
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ppi_ch1.enable();
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let mut ppi_ch2 = Ppi::new_one_to_one(
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ppi_ch2.degrade(),
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timer.cc(0).event_compare(),
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Task::from_reg(&r.tasks_stoprx),
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);
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ppi_ch2.enable();
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Self {
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inner: PeripheralMutex::new(irq, &mut state.0, move || StateInner {
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phantom: PhantomData,
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timer,
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_ppi_ch1: ppi_ch1,
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_ppi_ch2: ppi_ch2,
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rx: RingBuffer::new(rx_buffer),
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rx_state: RxState::Idle,
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rx_waker: WakerRegistration::new(),
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tx: RingBuffer::new(tx_buffer),
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tx_state: TxState::Idle,
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tx_waker: WakerRegistration::new(),
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}),
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}
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}
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pub fn set_baudrate(&mut self, baudrate: Baudrate) {
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self.inner.with(|state| {
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let r = U::regs();
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let timeout = 0x8000_0000 / (baudrate as u32 / 40);
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state.timer.cc(0).write(timeout);
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state.timer.clear();
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r.baudrate.write(|w| w.baudrate().variant(baudrate));
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});
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}
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}
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impl<'d, U: UarteInstance, T: TimerInstance> embedded_io::Io for BufferedUarte<'d, U, T> {
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type Error = core::convert::Infallible;
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}
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impl<'d, U: UarteInstance, T: TimerInstance> embedded_io::asynch::Read for BufferedUarte<'d, U, T> {
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type ReadFuture<'a> = impl Future<Output = Result<usize, Self::Error>>
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where
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Self: 'a;
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fn read<'a>(&'a mut self, buf: &'a mut [u8]) -> Self::ReadFuture<'a> {
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poll_fn(move |cx| {
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let mut do_pend = false;
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let res = self.inner.with(|state| {
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compiler_fence(Ordering::SeqCst);
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trace!("poll_read");
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// We have data ready in buffer? Return it.
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let data = state.rx.pop_buf();
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if !data.is_empty() {
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trace!(" got {:?} {:?}", data.as_ptr() as u32, data.len());
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let len = data.len().min(buf.len());
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buf[..len].copy_from_slice(&data[..len]);
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state.rx.pop(len);
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do_pend = true;
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return Poll::Ready(Ok(len));
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}
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trace!(" empty");
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state.rx_waker.register(cx.waker());
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Poll::Pending
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});
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if do_pend {
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self.inner.pend();
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}
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res
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})
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}
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}
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impl<'d, U: UarteInstance, T: TimerInstance> embedded_io::asynch::BufRead for BufferedUarte<'d, U, T> {
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type FillBufFuture<'a> = impl Future<Output = Result<&'a [u8], Self::Error>>
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where
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Self: 'a;
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fn fill_buf<'a>(&'a mut self) -> Self::FillBufFuture<'a> {
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poll_fn(move |cx| {
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self.inner.with(|state| {
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compiler_fence(Ordering::SeqCst);
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trace!("fill_buf");
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// We have data ready in buffer? Return it.
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let buf = state.rx.pop_buf();
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if !buf.is_empty() {
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trace!(" got {:?} {:?}", buf.as_ptr() as u32, buf.len());
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let buf: &[u8] = buf;
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// Safety: buffer lives as long as uart
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let buf: &[u8] = unsafe { core::mem::transmute(buf) };
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return Poll::Ready(Ok(buf));
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}
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trace!(" empty");
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state.rx_waker.register(cx.waker());
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Poll::<Result<&[u8], Self::Error>>::Pending
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})
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})
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}
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fn consume(&mut self, amt: usize) {
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let signal = self.inner.with(|state| {
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let full = state.rx.is_full();
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state.rx.pop(amt);
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full
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});
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if signal {
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self.inner.pend();
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}
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}
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}
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impl<'d, U: UarteInstance, T: TimerInstance> embedded_io::asynch::Write for BufferedUarte<'d, U, T> {
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type WriteFuture<'a> = impl Future<Output = Result<usize, Self::Error>>
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where
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Self: 'a;
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fn write<'a>(&'a mut self, buf: &'a [u8]) -> Self::WriteFuture<'a> {
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poll_fn(move |cx| {
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let res = self.inner.with(|state| {
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trace!("poll_write: {:?}", buf.len());
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let tx_buf = state.tx.push_buf();
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if tx_buf.is_empty() {
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trace!("poll_write: pending");
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state.tx_waker.register(cx.waker());
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return Poll::Pending;
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}
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let n = min(tx_buf.len(), buf.len());
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tx_buf[..n].copy_from_slice(&buf[..n]);
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state.tx.push(n);
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trace!("poll_write: queued {:?}", n);
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compiler_fence(Ordering::SeqCst);
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Poll::Ready(Ok(n))
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});
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self.inner.pend();
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res
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})
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}
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type FlushFuture<'a> = impl Future<Output = Result<(), Self::Error>>
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where
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Self: 'a;
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fn flush<'a>(&'a mut self) -> Self::FlushFuture<'a> {
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poll_fn(move |cx| {
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self.inner.with(|state| {
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trace!("poll_flush");
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if !state.tx.is_empty() {
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trace!("poll_flush: pending");
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state.tx_waker.register(cx.waker());
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return Poll::Pending;
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}
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Poll::Ready(Ok(()))
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})
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})
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}
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}
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impl<'a, U: UarteInstance, T: TimerInstance> Drop for StateInner<'a, U, T> {
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fn drop(&mut self) {
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let r = U::regs();
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// TODO this probably deadlocks. do like Uarte instead.
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self.timer.stop();
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if let RxState::Receiving = self.rx_state {
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r.tasks_stoprx.write(|w| unsafe { w.bits(1) });
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}
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if let TxState::Transmitting(_) = self.tx_state {
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r.tasks_stoptx.write(|w| unsafe { w.bits(1) });
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}
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if let RxState::Receiving = self.rx_state {
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low_power_wait_until(|| r.events_endrx.read().bits() == 1);
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}
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if let TxState::Transmitting(_) = self.tx_state {
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low_power_wait_until(|| r.events_endtx.read().bits() == 1);
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}
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}
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}
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impl<'a, U: UarteInstance, T: TimerInstance> PeripheralState for StateInner<'a, U, T> {
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type Interrupt = U::Interrupt;
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fn on_interrupt(&mut self) {
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trace!("irq: start");
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let r = U::regs();
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loop {
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match self.rx_state {
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RxState::Idle => {
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trace!(" irq_rx: in state idle");
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let buf = self.rx.push_buf();
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if !buf.is_empty() {
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trace!(" irq_rx: starting {:?}", buf.len());
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self.rx_state = RxState::Receiving;
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// Set up the DMA read
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r.rxd.ptr.write(|w|
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// The PTR field is a full 32 bits wide and accepts the full range
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// of values.
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unsafe { w.ptr().bits(buf.as_ptr() as u32) });
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r.rxd.maxcnt.write(|w|
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// We're giving it the length of the buffer, so no danger of
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// accessing invalid memory. We have verified that the length of the
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// buffer fits in an `u8`, so the cast to `u8` is also fine.
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//
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// The MAXCNT field is at least 8 bits wide and accepts the full
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// range of values.
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unsafe { w.maxcnt().bits(buf.len() as _) });
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trace!(" irq_rx: buf {:?} {:?}", buf.as_ptr() as u32, buf.len());
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// Start UARTE Receive transaction
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r.tasks_startrx.write(|w| unsafe { w.bits(1) });
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}
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break;
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}
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RxState::Receiving => {
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trace!(" irq_rx: in state receiving");
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if r.events_endrx.read().bits() != 0 {
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self.timer.stop();
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let n: usize = r.rxd.amount.read().amount().bits() as usize;
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trace!(" irq_rx: endrx {:?}", n);
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self.rx.push(n);
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r.events_endrx.reset();
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self.rx_waker.wake();
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self.rx_state = RxState::Idle;
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} else {
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break;
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}
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}
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}
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}
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loop {
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match self.tx_state {
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TxState::Idle => {
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trace!(" irq_tx: in state Idle");
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let buf = self.tx.pop_buf();
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if !buf.is_empty() {
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trace!(" irq_tx: starting {:?}", buf.len());
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self.tx_state = TxState::Transmitting(buf.len());
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// Set up the DMA write
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r.txd.ptr.write(|w|
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// The PTR field is a full 32 bits wide and accepts the full range
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// of values.
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unsafe { w.ptr().bits(buf.as_ptr() as u32) });
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r.txd.maxcnt.write(|w|
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// We're giving it the length of the buffer, so no danger of
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// accessing invalid memory. We have verified that the length of the
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// buffer fits in an `u8`, so the cast to `u8` is also fine.
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//
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// The MAXCNT field is 8 bits wide and accepts the full range of
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// values.
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unsafe { w.maxcnt().bits(buf.len() as _) });
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// Start UARTE Transmit transaction
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r.tasks_starttx.write(|w| unsafe { w.bits(1) });
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}
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break;
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}
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TxState::Transmitting(n) => {
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trace!(" irq_tx: in state Transmitting");
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if r.events_endtx.read().bits() != 0 {
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r.events_endtx.reset();
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trace!(" irq_tx: endtx {:?}", n);
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self.tx.pop(n);
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self.tx_waker.wake();
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self.tx_state = TxState::Idle;
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} else {
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break;
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}
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}
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}
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}
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trace!("irq: end");
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}
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}
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