forked from Mirror/Ryujinx
54 lines
1.7 KiB
C#
54 lines
1.7 KiB
C#
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using ChocolArm64.Instruction;
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using ChocolArm64.State;
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namespace ChocolArm64.Decoder
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{
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class AOpCodeSimdMemMult : AOpCode, IAOpCodeSimd
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{
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public int Rt { get; private set; }
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public int Rn { get; private set; }
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public int Size { get; private set; }
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public int Rm { get; private set; }
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public int Reps { get; private set; }
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public int SElems { get; private set; }
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public int Elems { get; private set; }
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public bool WBack { get; private set; }
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public AOpCodeSimdMemMult(AInst Inst, long Position, int OpCode) : base(Inst, Position)
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{
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switch ((OpCode >> 12) & 0xf)
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{
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case 0b0000: Reps = 1; SElems = 4; break;
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case 0b0010: Reps = 4; SElems = 1; break;
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case 0b0100: Reps = 1; SElems = 3; break;
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case 0b0110: Reps = 3; SElems = 1; break;
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case 0b0111: Reps = 1; SElems = 1; break;
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case 0b1000: Reps = 1; SElems = 2; break;
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case 0b1010: Reps = 2; SElems = 1; break;
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default: Inst = AInst.Undefined; return;
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}
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Rt = (OpCode >> 0) & 0x1f;
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Rn = (OpCode >> 5) & 0x1f;
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Size = (OpCode >> 10) & 0x3;
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Rm = (OpCode >> 16) & 0x1f;
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WBack = ((OpCode >> 23) & 0x1) != 0;
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bool Q = ((OpCode >> 30) & 1) != 0;
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if (!Q && Size == 3 && SElems != 1)
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{
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Inst = AInst.Undefined;
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return;
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}
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RegisterSize = Q
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? ARegisterSize.SIMD128
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: ARegisterSize.SIMD64;
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Elems = (GetBitsCount() >> 3) >> Size;
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}
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}
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}
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