Commit graph

1047 commits

Author SHA1 Message Date
LDj3SNuD
1de16f7653
Add Fcvtas_S/V & Fcvtau_S/V. (#1018) 2020-03-24 22:53:49 +01:00
Chenj168
d0960e75aa
Fix the item name cannot be displayed in profiler view. (#1021) 2020-03-24 18:48:03 +01:00
Thog
e590262531
friends: Stub GetBlockedUserListIds (#1017) 2020-03-23 22:19:45 +01:00
Ac_K
b2d307d34f
Fix Prepo parsing reports (#1016)
This fix the parsing of prepo service reports which could failed in some edge case. I've improved the parsing of the object to a JSON string too.
2020-03-23 21:58:41 +01:00
gdkchan
6edc929894
Implement ICMP shader instruction (#1010) 2020-03-23 17:32:30 +01:00
gdkchan
9a208c4fb5
Keep sRGB enabled for texture blits (#1009) 2020-03-23 09:34:26 +11:00
gdkchan
49d7b1c7d8
Implement textureQueryLevels (#1007) 2020-03-23 08:31:31 +11:00
Chenj168
31b94f4641
Move the MakeOp to OpCodeTable class, for reduce the use of ConcurrentDictionary (#996) 2020-03-20 15:15:37 +11:00
gdkchan
8e64984158
Support partial invalidation on texture access (#1000)
* Support partial invalidation on texture access

* Fix typo

* PR feedback

* Fix modified size clamping
2020-03-20 14:17:11 +11:00
Ac_K
32d3f3f690
Implement GetRegionCode and add the RegionCode to settings (#999)
This implement `GetRegionCode` accordingly to RE. I've added a setting in the GUI and a field in the Configuration file with a way to update the Configuration file if needed.
2020-03-20 09:37:55 +11:00
Chenj168
561d64e5bf
Modify TranslatedFunction.GetPointer () to optimize performance (#995)
* add local var to reduce calling Marshal.GetFunctionPointerForDelegate

* modify code style
2020-03-20 09:11:20 +11:00
riperiperi
8226997bc7
CodeGen Optimisations (LSRA and Translator) (#978)
* Start of JIT garbage collection improvements

- thread static pool for Operand, MemoryOperand, Operation
- Operands and Operations are always to be constructed via their static
helper classes, so they can be pooled.
- removing LinkedList from Node for sources/destinations (replaced with
List<>s for now, but probably could do arrays since size is bounded)
- removing params constructors from Node
- LinkedList<> to List<> with Clear() for Operand assignments/uses
- ThreadStaticPool is very simple and basically just exists for the
purpose of our specific translation allocation problem. Right now it
will stay at the worst case allocation count for that thread (so far) -
the pool can never shrink.

- Still some cases of Operand[] that haven't been removed yet. Will need
to evaluate them (eg. is there a reasonable max number of params for
Calls?)

* ConcurrentStack instead of ConcurrentQueue for Rejit

* Optimize some parts of LSRA

- BitMap now operates on 64-bit int rather than 32-bit
- BitMap is now pooled in a ThreadStatic pool (within lrsa)
- BitMap now is now its own iterator. Marginally speeds up iterating
through the bits.
- A few cases where enumerators were generated have been converted to
forms that generate less garbage.
- New data structure for sorting _usePositions in LiveIntervals. Much
faster split, NextUseAfter, initial insertion. Random insertion is
slightly slower.
- That last one is WIP since you need to insert the values backwards. It
would be ideal if it just flipped it for you, uncomplicating things on
the caller side.

* Use a static pool of thread static pools. (yes.)

Prevents each execution thread creating its own lowCq pool and making me cry.

* Move constant value to top, change naming convention.

* Fix iteration of memory operands.

* Increase max thread count.

* Address Feedback
2020-03-18 22:44:32 +11:00
Thog
7475e180b4
audren: Accept REV8 (#993)
REV8 only added changes on performance buffer and wavebuffer dsp command
generation.

As we don't support any of those, we can just increment the revision
number for now.
2020-03-18 09:43:47 +11:00
gdkchan
8bb64ac69c
Improve shader sampler type selection (#989) 2020-03-15 11:24:45 +11:00
riperiperi
8ce3993afa
Fix GTK window crash by using 24 bit surface on unix, 32 bit on windows. (#976)
* Use 24 bit surface on unix, 32 bit on windows.

* Address jd's comment

Co-authored-by: Thomas Guillemard <me@thog.eu>
2020-03-14 22:36:56 +01:00
riperiperi
dd433c1296
Implement AESMC, AESIMC, AESE, AESD and VEOR AArch32 instructions (#982)
* Add VEOR and AES instructions.

* Add tests for crypto instructions.

* Update ValueSource name.
2020-03-14 10:29:58 +11:00
gdkchan
ff2bac9c90
Implement MME shadow RAM (#987) 2020-03-13 12:30:26 +11:00
riperiperi
d904706fc0
Use a Jump Table for direct and indirect calls/jumps, removing transitions to managed (#975)
* Implement Jump Table for Native Calls

NOTE: this slows down rejit considerably! Not recommended to be used
without codegen optimisation or AOT.

- Does not work on Linux
- A32 needs an additional commit.

* A32 Support

(WIP)

* Actually write Direct Call pointers to the table

That would help.

* Direct Calls: Rather than returning to the translator, attempt to keep within the native stack frame.

A return to the translator can still happen, but only by exceptionally
bubbling up to it.

Also:
- Always translate lowCq as a function. Faster interop with the direct
jumps, and this will be useful in future if we want to do speculative
translation.
- Tail Call Detection: after the decoding stage, detect if we do a tail
call, and avoid translating into it. Detected if a jump is made to an
address outwith the contiguous sequence of blocks surrounding the entry
point. The goal is to reduce code touched by jit and rejit.

* A32 Support

* Use smaller max function size for lowCq, fix exceptional returns

When a return has an unexpected value and there is no code block
following this one, we now return the value rather than continuing.

* CompareAndSwap (buggy)

* Ensure CompareAndSwap does not get optimized away.

* Use CompareAndSwap to make the dynamic table thread safe.

* Tail call for linux, throw on too many arguments.

* Combine CompareAndSwap 128 and 32/64.

They emit different IR instructions since their PreAllocator behaviour
is different, but now they just have one function on EmitterContext.

* Fix issues separating from optimisations.

* Use a stub to find and execute missing functions.

This allows us to skip doing many runtime comparisons and branches, and reduces the amount of code we need to emit significantly.

For the indirect call table, this stub also does the work of moving in the highCq address to the table when one is found.

* Make Jump Tables and Jit Cache dynmically resize

Reserve virtual memory, commit as needed.

* Move TailCallRemover to its own class.

* Multithreaded Translation (based on heuristic)

A poor one, at that. Need to get core count for a better one, which
means a lot of OS specific garbage.

* Better priority management for background threads.

* Bound core limit a bit more

Past a certain point the load is not paralellizable and starts stealing from the main thread. Likely due to GC, memory, heap allocation thread contention. Reduce by one core til optimisations come to improve the situation.

* Fix memory management on linux.

* Temporary solution to some sync problems.

This will make sure threads exit correctly, most of the time. There is a potential race where setting the sync counter to 0 does nothing (counter stays at what it was before, thread could take too long to exit), but we need to find a better way to do this anyways. Synchronization frequency has been tightened as we never enter blockwise segments of code. Essentially this means, check every x functions or loop iterations, before lowcq blocks existed and were worth just as much. Ideally it should be done in a better way, since functions can be anywhere from 1 to 5000 instructions. (maybe based on host timer, or an interrupt flag from a scheduler thread)

* Address feedback minus CompareAndSwap change.

* Use default ReservedRegion granularity.

* Merge CompareAndSwap with its V128 variant.

* We already got the source, no need to do it again.

* Make sure all background translation threads exit.

* Fix CompareAndSwap128

Detection criteria was a bit scuffed.

* Address Comments.
2020-03-12 14:20:55 +11:00
gdkchan
c26f3774bd
Implement VMULL, VMLSL, VRSHR, VQRSHRN, VQRSHRUN AArch32 instructions + other fixes (#977)
* Implement VMULL, VMLSL, VQRSHRN, VQRSHRUN AArch32 instructions plus other fixes

* Re-align opcode table

* Re-enable undefined, use subclasses to fix checks

* Add test and fix VRSHR instruction

* PR feedback
2020-03-11 11:49:27 +11:00
gdkchan
89ccec197e
Implement VMOVL and VORR.I32 AArch32 SIMD instructions (#960)
* Implement VMOVL and VORR.I32 AArch32 SIMD instructions

* Rename <dt> to <size> on test description

* Rename Widen to Long and improve VMOVL implementation a bit
2020-03-10 16:17:30 +11:00
Alex Barney
08c0e3829b
Insert the SD card by default (#968) 2020-03-10 09:34:35 +11:00
gdkchan
61d79facd1
Optimize x64 loads and stores using complex addressing modes (#972)
* Optimize x64 loads and stores using complex addressing modes

* This was meant to be used for testing
2020-03-10 09:29:34 +11:00
Xpl0itR
e2bb5e8091
Move status information from the title bar to the new status bar (#948)
* Move status information from the title bar to the new status bar

* jd's requested changes

* Ack's requested changes

* gdk's requested changes

* Remove frame time statistics
2020-03-07 13:40:06 +11:00
gdkchan
ab3b6ea6d4
A64 SIMD LDP and STP with size = 0b11 is undefined (#971) 2020-03-07 13:39:52 +11:00
jduncanator
54501962f6
Fix branch with CC and predicate, and a case of SYNC propagation (#967) 2020-03-06 11:09:49 +11:00
jduncanator
68e15c1a74
Implement Fast Paths for most A32 SIMD instructions (#952)
* Begin work on A32 SIMD Intrinsics

* More instructions, some cleanup.

* Intrinsics for Move instructions (zip etc)

These pass the existing tests.

* Intrinsics for some of Cvt

While doing this I noticed that the conversion for int/fp was incorrect
in the slow path. I'll fix this in the original repo.

* Intrinsics for more Arithmetic instructions.

* Intrinsics for Vext

* Fix VEXT Intrinsic for double words.

* Use InsertPs to move scalar values.

* Cleanup, fix VPADD.f32 and VMIN signed integer.

* Cleanup, add SSE2 support for scalar insert.

Works similarly to the IR scalar insert, but obviously this one works
directly on V128.

* Minor cleanup.

* Enable intrinsic for FP64 to integer conversion.

* Address feedback apart from splitting out intrinsic float abs

Also: bad VREV encodings as undefined rather than throwing in translation.

* Move float abs to helper, fix bug with cvt

* Rename opc2 & 3 to match A32 docs, use ArgumentOutOfRangeException appropriately.

* Get name of variable at compilation rather than string literal.

* Use correct double sign mask.
2020-03-05 11:41:33 +11:00
gdkchan
d9ed827696
Don't decode blocks starting outside mapped memory & undefined instead of throw on invalid sysreg coprocessor (#964)
* Don't decode blocks in invalid memory locations.

* Emit undefined instruction on invalid coprocessor

...rather than throwing.

* Call undefined instruction directly.
2020-03-04 16:25:27 -03:00
Ac_K
25c3b8b356
Implement some calls of ISelfController (#965)
* Implement some calls of ISelfController

This PR implement some calls of ISelfController:

- EnterFatalSection
- LeaveFatalSection
- GetAccumulatedSuspendedTickValue (close #937)

According to RE of the 8.1.0 am service.

* thread safe increment/decrement

* Fix thread safe

* remove unused using
2020-03-04 00:41:41 -03:00
Alex Barney
cecbd256a5
Add support for cache storage (#936)
* Update LibHac

* Run EnsureApplicationCacheStorage when launching a game

* Add new FS commands
2020-03-03 15:07:06 +01:00
gdkchan
dc97457bf0
Initial support for double precision shader instructions. (#963)
* Implement DADD, DFMA and DMUL shader instructions

* Rename FP to FP32

* Correct double immediate

* Classic mistake
2020-03-03 15:02:08 +01:00
emmauss
3045c1a186
update glwidget package (#961) 2020-03-03 13:49:18 +11:00
Thog
47f079d23e
stub GetNintendoAccountUserResourceCacheForApplication (#962) 2020-03-03 01:07:27 +11:00
Thog
3b531de670
Implement mii:u and mii:e entirely (#955)
* Implement mii:u and mii:e entirely

Co-authored-by: AcK77 <Acoustik666@gmail.com>

This commit implement the mii service accurately.

This is based on Ac_k work but was polished and updated to 7.x.

Please note that the following calls are partially implemented:

- Convert: Used to convert from old console format (Wii/Wii U/3ds)
- Import and Export: this is shouldn't be accesible in production mode.

* Remove some debug leftovers

* Make it possible to load an arbitrary mii database from a Switch

* Address gdk's comments

* Reduce visibility of all the Mii code

* Address Ac_K's comments

* Remove the StructLayout of DatabaseSessionMetadata

* Add a missing line return in DatabaseSessionMetadata

* Misc fixes and style changes

* Fix some issues from last commit

* Fix database server metadata UpdateCounter in MarkDirty (Thanks Moose for the catch)

* MountCounter should only be incremented when no error is reported

* Fix FixDatabase

Co-authored-by: Alex Barney <thealexbarney@gmail.com>
2020-03-02 09:56:01 +11:00
gdkchan
7d1a294eae
Implement SMULWB, SMULWT, SMLAWB, SMLAWT (AArch32) (#953)
* Implement SMULWB, SMULWT, SMLAWB, SMLAWT, and add tests for some multiply instructions

* Improve test descriptions

* Rename SMULH to SMUL__

Co-authored-by: jduncanator <1518948+jduncanator@users.noreply.github.com>
2020-03-01 18:47:05 +11:00
gdkchan
fb0939f9b6
Add SSAT, SSAT16, USAT and USAT16 ARM32 instructions (#954)
* Implement SMULWB, SMULWT, SMLAWB, SMLAWT, and add tests for some multiply instructions

* Improve test descriptions

* Rename SMULH to SMUL__

* Add SSAT, SSAT16, USAT and USAT16 ARM32 instructions

* Fix new tests

* Replace AND 0xFFFF with 16-bits zero extension (more efficient)
2020-03-01 07:51:55 +11:00
gdkchan
b8ee5b15ab
Implement FACGE and FACGT (Scalar and Vector) AArch64 SIMD instructions (#956) 2020-03-01 07:51:17 +11:00
riperiperi
f35af5f703
Reduce copy destination size by target mipmap level, rather than source size. (#959)
* Change destination size by target mipmap level, rather than source.

* Check dst for Texture3D rather than src.
2020-03-01 07:50:44 +11:00
gdkchan
6204f0e47a
Set Undefined instruction emitter for Undefined property on InstDescriptor (#957) 2020-02-29 12:12:15 +01:00
riperiperi
b1b6f294f2
Add most of the A32 instruction set to ARMeilleure (#897)
* Implement TEQ and MOV (Imm16)

* Initial work on A32 instructions + SVC. No tests yet, hangs in rtld.

* Implement CLZ, fix BFI and BFC

Now stops on SIMD initialization.

* Exclusive access instructions, fix to mul, system instructions.

Now gets to a break after SignalProcessWideKey64.

* Better impl of UBFX, add UDIV and SDIV

Now boots way further - now stuck on VMOV instruction.

* Many more instructions, start on SIMD and testing framework.

* Fix build issues

* svc: Rework 32 bit codepath

Fixing once and for all argument ordering issues.

* Fix 32 bits stacktrace

* hle debug: Add 32 bits dynamic section parsing

* Fix highCq mode, add many tests, fix some instruction bugs

Still suffers from critical malloc failure 😩

* Fix incorrect opcode decoders and a few more instructions.

* Add a few instructions and fix others. re-disable highCq for now.

Disabled the svc memory clear since i'm not sure about it.

* Fix build

* Fix typo in ordered/exclusive stores.

* Implement some more instructions, fix others.

Uxtab16/Sxtab16 are untested.

* Begin impl of pairwise, some other instructions.

* Add a few more instructions, a quick hack to fix svcs for now.

* Add tests and fix issues with VTRN, VZIP, VUZP

* Add a few more instructions, fix Vmul_1 encoding.

* Fix way too many instruction bugs, add tests for some of the more important ones.

* Fix HighCq, enable FastFP paths for some floating point instructions

(not entirely sure why these were disabled, so important to note this
commit exists)

Branching has been removed in A32 shifts until I figure out if it's
worth it

* Cleanup Part 1

There should be no functional change between these next few commits.
Should is the key word. (except for removing break handler)

* Implement 32 bits syscalls

Co-authored-by: riperiperi <rhy3756547@hotmail.com>

Implement all 32 bits counterparts of the 64 bits syscalls we currently
have.

* Refactor part 2: Move index/subindex logic to Operand

May have inadvertently fixed one (1) bug

* Add FlushProcessDataCache32

* Address jd's comments

* Remove 16 bit encodings from OpCodeTable

Still need to catch some edge cases (operands that use the "F" flag) and
make Q encodings with non-even indexes undefined.

* Correct Fpscr handling for FP vector slow paths

WIP

* Add StandardFPSCRValue behaviour for all Arithmetic instructions

* Add StandardFPSCRValue behaviour to compare instructions.

* Force passing of fpcr to FPProcessException and FPUnpack.

Reduces potential for code error significantly

* OpCode cleanup

* Remove urgency from DMB comment in MRRC

DMB is currently a no-op via the instruction, so it should likely still
be a no-op here.

* Test Cleanup

* Fix FPDefaultNaN on Ryzen CPUs

* Improve some tests, fix some shift instructions, add slow path for Vadd

* Fix Typo

* More test cleanup

* Flip order of Fx and index, to indicate that the operand's is the "base"

* Remove Simd32 register type, use Int32 and Int64 for scalars like A64 does.

* Reintroduce alignment to DecoderHelper (removed by accident)

* One more realign as reading diffs is hard

* Use I32 registers in A32 (part 2)

Swap default integer register type based on current execution mode.

* FPSCR flags as Registers (part 1)

Still need to change NativeContext and ExecutionContext to allow
getting/setting with the flag values.

* Use I32 registers in A32 (part 1)

* FPSCR flags as registers (part 2)

Only CMP flags are on the registers right now. It could be useful to use
more of the space in non-fast-float when implementing A32 flags
accurately in the fast path.

* Address Feedback

* Correct FP->Int behaviour (should saturate)

* Make branches made by writing to PC eligible for Rejit

Greatly improves performance in most games.

* Remove unused branching for Vtbl

* RejitRequest as a class rather than a tuple

Makes a lot more sense than storing tuples on a dictionary.

* Add VMOVN, VSHR (imm), VSHRN (imm) and related tests

* Re-order InstEmitSystem32

Alphabetical sorting.

* Address Feedback

Feedback from Ac_K, remove and sort usings.

* Address Feedback 2

* Address Feedback from LDj3SNuD

Opcode table reordered to have alphabetical sorting within groups,
Vmaxnm and Vminnm have split names to be less ambiguous, SoftFloat nits,
Test nits and Test simplification with ValueSource.

* Add Debug Asserts to A32 helpers

Mainly to prevent the shift ones from being used on I64 operands, as
they expect I32 input for most operations (eg. carry flag setting), and
expect I32 input for shift and boolean amounts. Most other helper
functions don't take Operands, throw on out of range values, and take
specific types of OpCode, so didn't need any asserts.

* Use ConstF rather than creating an operand.

(useful for pooling in future)

* Move exclusive load to helper, reference call flag rather than literal 1.

* Address LDj feedback (minus table flatten)

one final look before it's all gone. the world is so beautiful.

* Flatten OpCodeTable

oh no

* Address more table ordering

* Call Flag as int on A32

Co-authored-by: Natalie C. <cyuubiapps@gmail.com>
Co-authored-by: Thog <thog@protonmail.com>
2020-02-24 08:20:40 +11:00
Alex Barney
165e658f02
Actually use the dummy NACP for EnsureApplicationSaveData (#939) 2020-02-18 22:35:47 +11:00
Thog
5f6949d9b0
Improve rendering on resolution lower than 1080p (#944)
* Improve rendering on resolution lower than 1080p

* Apply scaling factor to the renderer (This fix 4K displays)
2020-02-18 22:34:57 +11:00
Xpl0itR
d736352da2
Add button in settings to open logs folder (#947) 2020-02-17 22:35:03 +01:00
gdkchan
e5f78fb1d4
Replace LinkedList by IntrusiveList to avoid allocations on JIT (#931)
* Replace LinkedList by IntrusiveList to avoid allocations on JIT

* Fix wrong replacements
2020-02-17 22:30:54 +01:00
Thog
e9a37ca6a8
Implement GetCurrentIpConfigInfo (#943)
* Implement GetCurrentIpConfigInfo

This is needed by Rocket League.

Also fix GetCurrentIpConfigInfo to not return ipv6 addresses

* Address Ac_K comment
2020-02-17 16:28:41 +01:00
Xpl0itR
d89e90a16e
Catch System.IO.IOException (#932) 2020-02-15 21:20:19 +01:00
Thog
45d86b8f6f Retrigger Appveyor 2020-02-15 13:08:05 +01:00
Thog
91b37ae36e
Accept gamepad inputs when not focused (#941) 2020-02-15 12:30:53 +01:00
Thog
4789f79254
Fix crash when first starting the emulator (#945)
* Fix crash when first starting the emulator

* Fix a nit
2020-02-14 23:07:22 +01:00
Xpl0itR
a73fd9e9bd
Changes to configuration (#811)
* config loading changes

- load config from either ryufs or ryujinx.exe parent folder with parent folder taking priority
- config file in repo is only copied to parent directory if built in debug mode

* AcK's requested changes

* add "Profile Debug" as a condition to copy the default config to output
2020-02-14 20:19:13 +01:00
Thog
dbe3f938c7
Remove ScopedGlContext (#933)
As MakeCurrent can be slow to execute, this PR changes GLRenderer to not
have to reexecute MakeCurrent when processing frames.
2020-02-14 11:52:34 +01:00