R/ARMeilleure
sharmander e901b7850c
CPU: Implement VRINTX.F32 | VRINTX.F64 (#1776)
* Start implementation

* Draft

* Updated opcode.

Needs verification.

* Clean up code.

* Update implementation and tests.

* Update implemenation + tests

* Get RM from FPSCR + Do not use emit/addintrinsic

* Remove "fast" path, as recommended by gdk.

* Variable DELETED.

* Update ARMeilleure/Decoders/OpCodeTable.cs

Co-authored-by: LDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com>

* Update ARMeilleure/Instructions/InstEmitSimdCvt32.cs

Co-authored-by: LDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com>

* Update ARMeilleure/Instructions/InstEmitSimdCvt32.cs

Co-authored-by: LDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com>

* Update ARMeilleure/Instructions/InstEmitSimdCvt32.cs

Co-authored-by: LDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com>

* Move method

* stringing things together :)

Co-authored-by: LDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com>
2020-12-16 20:27:15 -03:00
..
CodeGen CPU: Implement VFMA (Vector) (#1762) 2020-12-15 00:01:52 -03:00
Common Clear JIT cache on exit (#1518) 2020-12-16 17:07:42 -03:00
Decoders CPU: Implement VRINTX.F32 | VRINTX.F64 (#1776) 2020-12-16 20:27:15 -03:00
Diagnostics Implement block placement (#1549) 2020-09-19 20:00:24 -03:00
Instructions CPU: Implement VRINTX.F32 | VRINTX.F64 (#1776) 2020-12-16 20:27:15 -03:00
IntermediateRepresentation CPU: Implement VFNMA.F32 | F.64 (#1783) 2020-12-07 21:04:01 -03:00
Memory Clear JIT cache on exit (#1518) 2020-12-16 17:07:42 -03:00
State IPC refactor part 2: Use ReplyAndReceive on HLE services and remove special handling from kernel (#1458) 2020-12-02 00:23:43 +01:00
Translation Clear JIT cache on exit (#1518) 2020-12-16 17:07:42 -03:00
ARMeilleure.csproj infra: Migrate to .NET 5 (#1694) 2020-11-15 19:27:15 +01:00
Optimizations.cs CPU: Implement VFNMS.F32/64 (#1758) 2020-12-03 20:20:02 +01:00
Statistics.cs Suppress warnings from fields never used or never assigned (CS0169 and CS0649) (#919) 2020-04-21 07:59:59 +10:00