forked from Mirror/Ryujinx
2421186d97
* Generalize tail continues * Fix DecodeBasicBlock `Next` and `Branch` would be null, which is not the state expected by the branch instructions. They end up branching or falling into a block which is never populated by the `Translator`. This causes an assert to be fired when building the CFG. * Clean up Decode overloads * Do not synchronize when branching into exit block If we're branching into an exit block, that exit block will tail continue into another translation which already has a synchronization. * Remove A32 predicate tail continue If `block` is not an exit block then the `block.Next` must exist (as per the last instruction of `block`). * Throw if decoded 0 blocks Address gdkchan's feedback * Rebuild block list instead of setting to null Address gdkchan's feedback
84 lines
No EOL
2.4 KiB
C#
84 lines
No EOL
2.4 KiB
C#
using ARMeilleure.Decoders;
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using ARMeilleure.IntermediateRepresentation;
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using ARMeilleure.State;
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using ARMeilleure.Translation;
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using static ARMeilleure.Instructions.InstEmitFlowHelper;
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using static ARMeilleure.Instructions.InstEmitHelper;
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using static ARMeilleure.IntermediateRepresentation.OperandHelper;
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namespace ARMeilleure.Instructions
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{
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static partial class InstEmit32
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{
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public static void B(ArmEmitterContext context)
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{
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IOpCode32BImm op = (IOpCode32BImm)context.CurrOp;
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context.Branch(context.GetLabel((ulong)op.Immediate));
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}
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public static void Bl(ArmEmitterContext context)
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{
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Blx(context, x: false);
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}
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public static void Blx(ArmEmitterContext context)
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{
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Blx(context, x: true);
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}
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private static void Blx(ArmEmitterContext context, bool x)
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{
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IOpCode32BImm op = (IOpCode32BImm)context.CurrOp;
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uint pc = op.GetPc();
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bool isThumb = IsThumb(context.CurrOp);
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uint currentPc = isThumb
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? pc | 1
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: pc - 4;
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SetIntA32(context, GetBankedRegisterAlias(context.Mode, RegisterAlias.Aarch32Lr), Const(currentPc));
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// If x is true, then this is a branch with link and exchange.
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// In this case we need to swap the mode between Arm <-> Thumb.
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if (x)
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{
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SetFlag(context, PState.TFlag, Const(isThumb ? 0 : 1));
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}
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EmitCall(context, (ulong)op.Immediate);
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}
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public static void Blxr(ArmEmitterContext context)
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{
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IOpCode32BReg op = (IOpCode32BReg)context.CurrOp;
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uint pc = op.GetPc();
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Operand addr = context.Copy(GetIntA32(context, op.Rm));
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Operand bitOne = context.BitwiseAnd(addr, Const(1));
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bool isThumb = IsThumb(context.CurrOp);
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uint currentPc = isThumb
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? pc | 1
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: pc - 4;
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SetIntA32(context, GetBankedRegisterAlias(context.Mode, RegisterAlias.Aarch32Lr), Const(currentPc));
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SetFlag(context, PState.TFlag, bitOne);
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EmitVirtualCall(context, addr);
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}
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public static void Bx(ArmEmitterContext context)
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{
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IOpCode32BReg op = (IOpCode32BReg)context.CurrOp;
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EmitBxWritePc(context, GetIntA32(context, op.Rm), op.Rm);
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}
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}
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} |