forked from Mirror/Ryujinx
6b23a2c125
* Start implementing a new shader translator * Fix shift instructions and a typo * Small refactoring on StructuredProgram, move RemovePhis method to a separate class * Initial geometry shader support * Implement TLD4 * Fix -- There's no negation on FMUL32I * Add constant folding and algebraic simplification optimizations, nits * Some leftovers from constant folding * Avoid cast for constant assignments * Add a branch elimination pass, and misc small fixes * Remove redundant branches, add expression propagation and other improvements on the code * Small leftovers -- add missing break and continue, remove unused properties, other improvements * Add null check to handle empty block cases on block visitor * Add HADD2 and HMUL2 half float shader instructions * Optimize pack/unpack sequences, some fixes related to half float instructions * Add TXQ, TLD, TLDS and TLD4S shader texture instructions, and some support for bindless textures, some refactoring on codegen * Fix copy paste mistake that caused RZ to be ignored on the AST instruction * Add workaround for conditional exit, and fix half float instruction with constant buffer * Add missing 0.0 source for TLDS.LZ variants * Simplify the switch for TLDS.LZ * Texture instructions related fixes * Implement the HFMA instruction, and some misc. fixes * Enable constant folding on UnpackHalf2x16 instructions * Refactor HFMA to use OpCode* for opcode decoding rather than on the helper methods * Remove the old shader translator * Remove ShaderDeclInfo and other unused things * Add dual vertex shader support * Add ShaderConfig, used to pass shader type and maximum cbuffer size * Move and rename some instruction enums * Move texture instructions into a separate file * Move operand GetExpression and locals management to OperandManager * Optimize opcode decoding using a simple list and binary search * Add missing condition for do-while on goto elimination * Misc. fixes on texture instructions * Simplify TLDS switch * Address PR feedback, and a nit
267 lines
No EOL
8 KiB
C#
267 lines
No EOL
8 KiB
C#
using Ryujinx.Graphics.Shader.Decoders;
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using Ryujinx.Graphics.Shader.IntermediateRepresentation;
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using Ryujinx.Graphics.Shader.Translation;
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using System;
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using static Ryujinx.Graphics.Shader.IntermediateRepresentation.OperandHelper;
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namespace Ryujinx.Graphics.Shader.Instructions
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{
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static class InstEmitHelper
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{
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public static Operand GetZF(EmitterContext context)
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{
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return Register(0, RegisterType.Flag);
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}
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public static Operand GetNF(EmitterContext context)
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{
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return Register(1, RegisterType.Flag);
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}
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public static Operand GetCF(EmitterContext context)
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{
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return Register(2, RegisterType.Flag);
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}
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public static Operand GetVF(EmitterContext context)
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{
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return Register(3, RegisterType.Flag);
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}
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public static Operand GetDest(EmitterContext context)
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{
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return Register(((IOpCodeRd)context.CurrOp).Rd);
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}
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public static Operand GetSrcA(EmitterContext context)
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{
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return Register(((IOpCodeRa)context.CurrOp).Ra);
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}
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public static Operand GetSrcB(EmitterContext context, FPType floatType)
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{
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if (floatType == FPType.FP32)
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{
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return GetSrcB(context);
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}
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else if (floatType == FPType.FP16)
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{
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int h = context.CurrOp.RawOpCode.Extract(41, 1);
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return GetHalfSources(context, GetSrcB(context), FPHalfSwizzle.FP16)[h];
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}
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else if (floatType == FPType.FP64)
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{
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//TODO.
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}
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throw new ArgumentException($"Invalid floating point type \"{floatType}\".");
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}
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public static Operand GetSrcB(EmitterContext context)
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{
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switch (context.CurrOp)
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{
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case IOpCodeCbuf op:
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return Cbuf(op.Slot, op.Offset);
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case IOpCodeImm op:
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return Const(op.Immediate);
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case IOpCodeImmF op:
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return ConstF(op.Immediate);
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case IOpCodeReg op:
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return Register(op.Rb);
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case IOpCodeRegCbuf op:
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return Register(op.Rc);
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}
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throw new InvalidOperationException($"Unexpected opcode type \"{context.CurrOp.GetType().Name}\".");
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}
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public static Operand GetSrcC(EmitterContext context)
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{
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switch (context.CurrOp)
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{
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case IOpCodeRegCbuf op:
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return Cbuf(op.Slot, op.Offset);
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case IOpCodeRc op:
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return Register(op.Rc);
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}
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throw new InvalidOperationException($"Unexpected opcode type \"{context.CurrOp.GetType().Name}\".");
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}
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public static Operand[] GetHalfSrcA(EmitterContext context)
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{
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OpCode op = context.CurrOp;
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bool absoluteA = false, negateA = false;
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if (op is IOpCodeCbuf || op is IOpCodeImm)
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{
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negateA = op.RawOpCode.Extract(43);
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absoluteA = op.RawOpCode.Extract(44);
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}
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else if (op is IOpCodeReg)
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{
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absoluteA = op.RawOpCode.Extract(44);
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}
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else if (op is OpCodeAluImm32 && op.Emitter == InstEmit.Hadd2)
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{
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negateA = op.RawOpCode.Extract(56);
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}
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FPHalfSwizzle swizzle = (FPHalfSwizzle)op.RawOpCode.Extract(47, 2);
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Operand[] operands = GetHalfSources(context, GetSrcA(context), swizzle);
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return FPAbsNeg(context, operands, absoluteA, negateA);
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}
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public static Operand[] GetHalfSrcB(EmitterContext context)
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{
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OpCode op = context.CurrOp;
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FPHalfSwizzle swizzle = FPHalfSwizzle.FP16;
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bool absoluteB = false, negateB = false;
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if (op is IOpCodeReg)
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{
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swizzle = (FPHalfSwizzle)op.RawOpCode.Extract(28, 2);
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absoluteB = op.RawOpCode.Extract(30);
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negateB = op.RawOpCode.Extract(31);
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}
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else if (op is IOpCodeCbuf)
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{
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swizzle = FPHalfSwizzle.FP32;
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absoluteB = op.RawOpCode.Extract(54);
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}
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Operand[] operands = GetHalfSources(context, GetSrcB(context), swizzle);
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return FPAbsNeg(context, operands, absoluteB, negateB);
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}
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public static Operand[] FPAbsNeg(EmitterContext context, Operand[] operands, bool abs, bool neg)
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{
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for (int index = 0; index < operands.Length; index++)
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{
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operands[index] = context.FPAbsNeg(operands[index], abs, neg);
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}
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return operands;
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}
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public static Operand[] GetHalfSources(EmitterContext context, Operand src, FPHalfSwizzle swizzle)
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{
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switch (swizzle)
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{
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case FPHalfSwizzle.FP16:
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return new Operand[]
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{
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context.UnpackHalf2x16Low (src),
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context.UnpackHalf2x16High(src)
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};
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case FPHalfSwizzle.FP32: return new Operand[] { src, src };
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case FPHalfSwizzle.DupH0:
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return new Operand[]
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{
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context.UnpackHalf2x16Low(src),
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context.UnpackHalf2x16Low(src)
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};
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case FPHalfSwizzle.DupH1:
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return new Operand[]
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{
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context.UnpackHalf2x16High(src),
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context.UnpackHalf2x16High(src)
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};
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}
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throw new ArgumentException($"Invalid swizzle \"{swizzle}\".");
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}
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public static Operand GetHalfPacked(EmitterContext context, Operand[] results)
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{
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OpCode op = context.CurrOp;
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FPHalfSwizzle swizzle = FPHalfSwizzle.FP16;
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if (!(op is OpCodeAluImm32))
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{
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swizzle = (FPHalfSwizzle)context.CurrOp.RawOpCode.Extract(49, 2);
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}
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switch (swizzle)
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{
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case FPHalfSwizzle.FP16: return context.PackHalf2x16(results[0], results[1]);
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case FPHalfSwizzle.FP32: return results[0];
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case FPHalfSwizzle.DupH0:
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{
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Operand h1 = GetHalfDest(context, isHigh: true);
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return context.PackHalf2x16(results[0], h1);
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}
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case FPHalfSwizzle.DupH1:
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{
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Operand h0 = GetHalfDest(context, isHigh: false);
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return context.PackHalf2x16(h0, results[1]);
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}
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}
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throw new ArgumentException($"Invalid swizzle \"{swizzle}\".");
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}
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public static Operand GetHalfDest(EmitterContext context, bool isHigh)
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{
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if (isHigh)
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{
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return context.UnpackHalf2x16High(GetDest(context));
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}
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else
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{
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return context.UnpackHalf2x16Low(GetDest(context));
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}
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}
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public static Operand GetPredicate39(EmitterContext context)
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{
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IOpCodeAlu op = (IOpCodeAlu)context.CurrOp;
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Operand local = Register(op.Predicate39);
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if (op.InvertP)
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{
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local = context.BitwiseNot(local);
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}
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return local;
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}
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public static Operand SignExtendTo32(EmitterContext context, Operand src, int srcBits)
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{
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return context.BitfieldExtractS32(src, Const(0), Const(srcBits));
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}
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public static Operand ZeroExtendTo32(EmitterContext context, Operand src, int srcBits)
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{
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int mask = (int)(0xffffffffu >> (32 - srcBits));
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return context.BitwiseAnd(src, Const(mask));
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}
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}
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} |