R/Ryujinx.Graphics/Graphics3d/NvGpuEngineM2mf.cs
Thomas Guillemard 884b4e5fd3 Initial non 2D textures support (#525)
* Initial non 2D textures support

- Shaders still need to be changed
- Some types aren't yet implemented

* Start implementing texture instructions suffixes

Fix wrong texture type with cube and TEXS

Also support array textures in TEX and TEX.B

Clean up TEX and TEXS coords managment

Fix TEXS.LL with non-2d textures

Implement TEX.AOFFI

Get the right arguments for TEX, TEXS and TLDS

Also, store suffix operands in appropriate values to support multiple
suffix combinaisons

* Support depth in read/writeTexture

Also support WrapR and detect mipmap

* Proper cube map textures support + fix TEXS.LZ

* Implement depth compare

* some code clean up

* Implement CubeMap textures in OGLTexture.Create

* Implement TLD4 and TLD4S

* Add Texture 1D support

* updates comments

* fix some code style issues

* Fix some nits + rename some things to be less confusing

* Remove GetSuffix local functions

* AOFFI => AOffI

* TextureType => GalTextureTarget

* finish renaming TextureType to TextureTarget

* Disable LL, LZ and LB support in the decompiler

This needs more work at the GL level (GLSL implementation should be
right)

* Revert "Disable LL, LZ and LB support in the decompiler"

This reverts commit 64536c3d9f673645faff3152838d1413c3203395.

* Fix TEXS ARRAY_2D index

* ImageFormat depth should be 1 for all image format

* Fix shader build issues with sampler1DShadow and texture

* Fix DC & AOFFI combinaison with TEX/TEXS

* Support AOFFI with TLD4 and TLD4S

* Fix shader compilation error for TLD4.AOFFI with no DC

* Fix binding isuses on the 2d copy engine

TODO: support 2d array copy

* Support 2D array copy operation in the 2D engine

This make every copy right in the GPU side.
Thie CPU copy probably needs to be updated

* Implement GetGpuSize + fix somes issues with 2d engine copies

TODO: mipmap level in it

* Don't throw an exception in the layer handling

* Fix because of rebase

* Reject 2d layers of non textures in 2d copy engine

* Add 3D textures and mipmap support on BlockLinearSwizzle

* Fix naming on new BitUtils methods

* gpu cache: Make sure to invalidate textures that doesn't have the same target

* Add the concept of layer count for array instead of using depth

Also cleanup GetGpuSize as Swizzle can compute the size with mipmap

* Support multi layer with mip map in ReadTexture

* Add more check for cache invalidation & remove cubemap and cubemap array code for now

Also fix compressed 2d array

* Fix texelFetchOffset shader build error

* Start looking into cube map again

Also add some way to log write in register in engines

* fix write register log levles

* Remove debug logs in WriteRegister

* Disable AOFFI support on non NVIDIA drivers

* Fix code align
2019-02-28 12:12:24 +11:00

196 lines
No EOL
6.5 KiB
C#

using Ryujinx.Common.Logging;
using Ryujinx.Graphics.Memory;
using Ryujinx.Graphics.Texture;
using System.Collections.Generic;
namespace Ryujinx.Graphics.Graphics3d
{
class NvGpuEngineM2mf : INvGpuEngine
{
public int[] Registers { get; private set; }
private NvGpu Gpu;
private Dictionary<int, NvGpuMethod> Methods;
public NvGpuEngineM2mf(NvGpu Gpu)
{
this.Gpu = Gpu;
Registers = new int[0x1d6];
Methods = new Dictionary<int, NvGpuMethod>();
void AddMethod(int Meth, int Count, int Stride, NvGpuMethod Method)
{
while (Count-- > 0)
{
Methods.Add(Meth, Method);
Meth += Stride;
}
}
AddMethod(0xc0, 1, 1, Execute);
}
public void CallMethod(NvGpuVmm Vmm, GpuMethodCall MethCall)
{
if (Methods.TryGetValue(MethCall.Method, out NvGpuMethod Method))
{
Method(Vmm, MethCall);
}
else
{
WriteRegister(MethCall);
}
}
private void Execute(NvGpuVmm Vmm, GpuMethodCall MethCall)
{
//TODO: Some registers and copy modes are still not implemented.
int Control = MethCall.Argument;
bool SrcLinear = ((Control >> 7) & 1) != 0;
bool DstLinear = ((Control >> 8) & 1) != 0;
bool Copy2d = ((Control >> 9) & 1) != 0;
long SrcAddress = MakeInt64From2xInt32(NvGpuEngineM2mfReg.SrcAddress);
long DstAddress = MakeInt64From2xInt32(NvGpuEngineM2mfReg.DstAddress);
int SrcPitch = ReadRegister(NvGpuEngineM2mfReg.SrcPitch);
int DstPitch = ReadRegister(NvGpuEngineM2mfReg.DstPitch);
int XCount = ReadRegister(NvGpuEngineM2mfReg.XCount);
int YCount = ReadRegister(NvGpuEngineM2mfReg.YCount);
int Swizzle = ReadRegister(NvGpuEngineM2mfReg.Swizzle);
int DstBlkDim = ReadRegister(NvGpuEngineM2mfReg.DstBlkDim);
int DstSizeX = ReadRegister(NvGpuEngineM2mfReg.DstSizeX);
int DstSizeY = ReadRegister(NvGpuEngineM2mfReg.DstSizeY);
int DstSizeZ = ReadRegister(NvGpuEngineM2mfReg.DstSizeZ);
int DstPosXY = ReadRegister(NvGpuEngineM2mfReg.DstPosXY);
int DstPosZ = ReadRegister(NvGpuEngineM2mfReg.DstPosZ);
int SrcBlkDim = ReadRegister(NvGpuEngineM2mfReg.SrcBlkDim);
int SrcSizeX = ReadRegister(NvGpuEngineM2mfReg.SrcSizeX);
int SrcSizeY = ReadRegister(NvGpuEngineM2mfReg.SrcSizeY);
int SrcSizeZ = ReadRegister(NvGpuEngineM2mfReg.SrcSizeZ);
int SrcPosXY = ReadRegister(NvGpuEngineM2mfReg.SrcPosXY);
int SrcPosZ = ReadRegister(NvGpuEngineM2mfReg.SrcPosZ);
int SrcCpp = ((Swizzle >> 20) & 7) + 1;
int DstCpp = ((Swizzle >> 24) & 7) + 1;
int DstPosX = (DstPosXY >> 0) & 0xffff;
int DstPosY = (DstPosXY >> 16) & 0xffff;
int SrcPosX = (SrcPosXY >> 0) & 0xffff;
int SrcPosY = (SrcPosXY >> 16) & 0xffff;
int SrcBlockHeight = 1 << ((SrcBlkDim >> 4) & 0xf);
int DstBlockHeight = 1 << ((DstBlkDim >> 4) & 0xf);
long SrcPA = Vmm.GetPhysicalAddress(SrcAddress);
long DstPA = Vmm.GetPhysicalAddress(DstAddress);
if (Copy2d)
{
if (SrcLinear)
{
SrcPosX = SrcPosY = SrcPosZ = 0;
}
if (DstLinear)
{
DstPosX = DstPosY = DstPosZ = 0;
}
if (SrcLinear && DstLinear)
{
for (int Y = 0; Y < YCount; Y++)
{
int SrcOffset = (SrcPosY + Y) * SrcPitch + SrcPosX * SrcCpp;
int DstOffset = (DstPosY + Y) * DstPitch + DstPosX * DstCpp;
long Src = SrcPA + (uint)SrcOffset;
long Dst = DstPA + (uint)DstOffset;
Vmm.Memory.CopyBytes(Src, Dst, XCount * SrcCpp);
}
}
else
{
ISwizzle SrcSwizzle;
if (SrcLinear)
{
SrcSwizzle = new LinearSwizzle(SrcPitch, SrcCpp, SrcSizeX, SrcSizeY);
}
else
{
SrcSwizzle = new BlockLinearSwizzle(
SrcSizeX,
SrcSizeY, 1,
SrcBlockHeight, 1,
SrcCpp);
}
ISwizzle DstSwizzle;
if (DstLinear)
{
DstSwizzle = new LinearSwizzle(DstPitch, DstCpp, SrcSizeX, SrcSizeY);
}
else
{
DstSwizzle = new BlockLinearSwizzle(
DstSizeX,
DstSizeY, 1,
DstBlockHeight, 1,
DstCpp);
}
for (int Y = 0; Y < YCount; Y++)
for (int X = 0; X < XCount; X++)
{
int SrcOffset = SrcSwizzle.GetSwizzleOffset(SrcPosX + X, SrcPosY + Y, 0);
int DstOffset = DstSwizzle.GetSwizzleOffset(DstPosX + X, DstPosY + Y, 0);
long Src = SrcPA + (uint)SrcOffset;
long Dst = DstPA + (uint)DstOffset;
Vmm.Memory.CopyBytes(Src, Dst, SrcCpp);
}
}
}
else
{
Vmm.Memory.CopyBytes(SrcPA, DstPA, XCount);
}
}
private long MakeInt64From2xInt32(NvGpuEngineM2mfReg Reg)
{
return
(long)Registers[(int)Reg + 0] << 32 |
(uint)Registers[(int)Reg + 1];
}
private void WriteRegister(GpuMethodCall MethCall)
{
Registers[MethCall.Method] = MethCall.Argument;
}
private int ReadRegister(NvGpuEngineM2mfReg Reg)
{
return Registers[(int)Reg];
}
private void WriteRegister(NvGpuEngineM2mfReg Reg, int Value)
{
Registers[(int)Reg] = Value;
}
}
}