JinxRyu/ChocolArm64/Decoders/IOpCode32BReg.cs

namespace ChocolArm64.Decoders
{
    interface IOpCode32BReg : IOpCode32
    {
        int Rm { get; }
    }
}
Add ARM32 support on the translator (#561) * Remove ARM32 interpreter and add ARM32 support on the translator * Nits. * Rename Cond -> Condition * Align code again * Rename Data to Alu * Enable ARM32 support and handle undefined instructions * Use the IsThumb method to check if its a thumb opcode * Remove another 32-bits check 2019-01-25 01:59:53 +00:00			`namespace ChocolArm64.Decoders`
			`{`
Implement some ARM32 memory instructions and CMP (#565) * Implement ARM32 memory instructions: LDM, LDR, LDRB, LDRD, LDRH, LDRSB, LDRSH, STM, STR, STRB, STRD, STRH (immediate and register + immediate variants), implement CMP (immediate and register shifted by immediate variants) * Rename some opcode classes and flag masks for consistency * Fix a few suboptimal ARM32 codegen issues, only loads should be considered on decoder when checking if Rt == PC, and only NZCV flags should be considered for comparison optimizations * Take into account Rt2 for LDRD instructions aswell when checking if the instruction changes PC * Re-align arm32 instructions on the opcode table 2019-01-29 16:06:11 +00:00			`interface IOpCode32BReg : IOpCode32`
Add ARM32 support on the translator (#561) * Remove ARM32 interpreter and add ARM32 support on the translator * Nits. * Rename Cond -> Condition * Align code again * Rename Data to Alu * Enable ARM32 support and handle undefined instructions * Use the IsThumb method to check if its a thumb opcode * Remove another 32-bits check 2019-01-25 01:59:53 +00:00			`{`
			`int Rm { get; }`
			`}`
			`}`