2019-02-11 12:00:32 +00:00
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{
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"$schema": "./_schema.json",
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// Dump shaders in local directory (e.g. `C:\ShaderDumps`)
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"graphics_shaders_dump_path": "",
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2019-07-02 02:39:22 +00:00
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// Enable printing debug logs
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2019-02-11 12:00:32 +00:00
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"logging_enable_debug": false,
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2019-07-02 02:39:22 +00:00
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// Enable printing stubbed calls logs
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2019-02-11 12:00:32 +00:00
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"logging_enable_stub": true,
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2019-07-02 02:39:22 +00:00
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// Enable printing information logs
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2019-02-11 12:00:32 +00:00
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"logging_enable_info": true,
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2019-07-02 02:39:22 +00:00
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// Enable printing warning logs
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2019-02-11 12:00:32 +00:00
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"logging_enable_warn": true,
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2019-07-02 02:39:22 +00:00
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// Enable printing error logs
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2019-02-11 12:00:32 +00:00
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"logging_enable_error": true,
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2019-06-16 01:31:18 +00:00
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// Enable printing guest logs
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"logging_enable_guest": true,
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Add a new JIT compiler for CPU code (#693)
* Start of the ARMeilleure project
* Refactoring around the old IRAdapter, now renamed to PreAllocator
* Optimize the LowestBitSet method
* Add CLZ support and fix CLS implementation
* Add missing Equals and GetHashCode overrides on some structs, misc small tweaks
* Implement the ByteSwap IR instruction, and some refactoring on the assembler
* Implement the DivideUI IR instruction and fix 64-bits IDIV
* Correct constant operand type on CSINC
* Move division instructions implementation to InstEmitDiv
* Fix destination type for the ConditionalSelect IR instruction
* Implement UMULH and SMULH, with new IR instructions
* Fix some issues with shift instructions
* Fix constant types for BFM instructions
* Fix up new tests using the new V128 struct
* Update tests
* Move DIV tests to a separate file
* Add support for calls, and some instructions that depends on them
* Start adding support for SIMD & FP types, along with some of the related ARM instructions
* Fix some typos and the divide instruction with FP operands
* Fix wrong method call on Clz_V
* Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes
* Implement SIMD logical instructions and more misc. fixes
* Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations
* Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes
* Implement SIMD shift instruction and fix Dup_V
* Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table
* Fix check with tolerance on tester
* Implement FP & SIMD comparison instructions, and some fixes
* Update FCVT (Scalar) encoding on the table to support the Half-float variants
* Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes
* Use old memory access methods, made a start on SIMD memory insts support, some fixes
* Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes
* Fix arguments count with struct return values, other fixes
* More instructions
* Misc. fixes and integrate LDj3SNuD fixes
* Update tests
* Add a faster linear scan allocator, unwinding support on windows, and other changes
* Update Ryujinx.HLE
* Update Ryujinx.Graphics
* Fix V128 return pointer passing, RCX is clobbered
* Update Ryujinx.Tests
* Update ITimeZoneService
* Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks
* Use generic GetFunctionPointerForDelegate method and other tweaks
* Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics
* Remove some unused code on the assembler
* Fix REX.W prefix regression on float conversion instructions, add some sort of profiler
* Add hardware capability detection
* Fix regression on Sha1h and revert Fcm** changes
* Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator
* Fix silly mistake introduced on last commit on CpuId
* Generate inline stack probes when the stack allocation is too large
* Initial support for the System-V ABI
* Support multiple destination operands
* Fix SSE2 VectorInsert8 path, and other fixes
* Change placement of XMM callee save and restore code to match other compilers
* Rename Dest to Destination and Inst to Instruction
* Fix a regression related to calls and the V128 type
* Add an extra space on comments to match code style
* Some refactoring
* Fix vector insert FP32 SSE2 path
* Port over the ARM32 instructions
* Avoid memory protection races on JIT Cache
* Another fix on VectorInsert FP32 (thanks to LDj3SNuD
* Float operands don't need to use the same register when VEX is supported
* Add a new register allocator, higher quality code for hot code (tier up), and other tweaks
* Some nits, small improvements on the pre allocator
* CpuThreadState is gone
* Allow changing CPU emulators with a config entry
* Add runtime identifiers on the ARMeilleure project
* Allow switching between CPUs through a config entry (pt. 2)
* Change win10-x64 to win-x64 on projects
* Update the Ryujinx project to use ARMeilleure
* Ensure that the selected register is valid on the hybrid allocator
* Allow exiting on returns to 0 (should fix test regression)
* Remove register assignments for most used variables on the hybrid allocator
* Do not use fixed registers as spill temp
* Add missing namespace and remove unneeded using
* Address PR feedback
* Fix types, etc
* Enable AssumeStrictAbiCompliance by default
* Ensure that Spill and Fill don't load or store any more than necessary
2019-08-08 18:56:22 +00:00
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2019-06-16 01:31:18 +00:00
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// Enable printing FS access logs. fs_global_access_log_mode must be 2 or 3
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"logging_enable_fs_access_log": false,
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2019-02-11 12:00:32 +00:00
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// Filtered log classes, in a JSON array, eg. `[ "Loader", "ServiceFs" ]`
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"logging_filtered_classes": [ ],
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// Enable file logging
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"enable_file_log": true,
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// Change System Language
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// System Language list: https://gist.github.com/HorrorTroll/b6e4a88d774c3c9b3bdf54d79a7ca43b
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"system_language": "AmericanEnglish",
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2019-02-28 02:03:31 +00:00
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// Enable or disable Docked Mode
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2019-02-11 12:00:32 +00:00
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"docked_mode": false,
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2019-02-28 02:03:31 +00:00
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2019-07-02 02:39:22 +00:00
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// Enable or disable Discord Rich Presence
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"enable_discord_integration": true,
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2019-05-30 20:27:43 +00:00
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2019-02-28 02:03:31 +00:00
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// Enable or disable Game Vsync
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2019-02-11 12:00:32 +00:00
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"enable_vsync": true,
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2019-02-28 02:03:31 +00:00
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// Enable or disable Multi-core scheduling of threads
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2019-02-18 23:52:06 +00:00
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"enable_multicore_scheduling": true,
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2019-02-28 02:03:31 +00:00
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2019-02-11 12:00:32 +00:00
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// Enable integrity checks on Switch content files
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"enable_fs_integrity_checks": true,
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2019-02-28 02:03:31 +00:00
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2019-06-16 01:31:18 +00:00
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// Sets the "GlobalAccessLogMode". Possible modes are 0-3
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"fs_global_access_log_mode": 0,
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Add a new JIT compiler for CPU code (#693)
* Start of the ARMeilleure project
* Refactoring around the old IRAdapter, now renamed to PreAllocator
* Optimize the LowestBitSet method
* Add CLZ support and fix CLS implementation
* Add missing Equals and GetHashCode overrides on some structs, misc small tweaks
* Implement the ByteSwap IR instruction, and some refactoring on the assembler
* Implement the DivideUI IR instruction and fix 64-bits IDIV
* Correct constant operand type on CSINC
* Move division instructions implementation to InstEmitDiv
* Fix destination type for the ConditionalSelect IR instruction
* Implement UMULH and SMULH, with new IR instructions
* Fix some issues with shift instructions
* Fix constant types for BFM instructions
* Fix up new tests using the new V128 struct
* Update tests
* Move DIV tests to a separate file
* Add support for calls, and some instructions that depends on them
* Start adding support for SIMD & FP types, along with some of the related ARM instructions
* Fix some typos and the divide instruction with FP operands
* Fix wrong method call on Clz_V
* Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes
* Implement SIMD logical instructions and more misc. fixes
* Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations
* Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes
* Implement SIMD shift instruction and fix Dup_V
* Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table
* Fix check with tolerance on tester
* Implement FP & SIMD comparison instructions, and some fixes
* Update FCVT (Scalar) encoding on the table to support the Half-float variants
* Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes
* Use old memory access methods, made a start on SIMD memory insts support, some fixes
* Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes
* Fix arguments count with struct return values, other fixes
* More instructions
* Misc. fixes and integrate LDj3SNuD fixes
* Update tests
* Add a faster linear scan allocator, unwinding support on windows, and other changes
* Update Ryujinx.HLE
* Update Ryujinx.Graphics
* Fix V128 return pointer passing, RCX is clobbered
* Update Ryujinx.Tests
* Update ITimeZoneService
* Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks
* Use generic GetFunctionPointerForDelegate method and other tweaks
* Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics
* Remove some unused code on the assembler
* Fix REX.W prefix regression on float conversion instructions, add some sort of profiler
* Add hardware capability detection
* Fix regression on Sha1h and revert Fcm** changes
* Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator
* Fix silly mistake introduced on last commit on CpuId
* Generate inline stack probes when the stack allocation is too large
* Initial support for the System-V ABI
* Support multiple destination operands
* Fix SSE2 VectorInsert8 path, and other fixes
* Change placement of XMM callee save and restore code to match other compilers
* Rename Dest to Destination and Inst to Instruction
* Fix a regression related to calls and the V128 type
* Add an extra space on comments to match code style
* Some refactoring
* Fix vector insert FP32 SSE2 path
* Port over the ARM32 instructions
* Avoid memory protection races on JIT Cache
* Another fix on VectorInsert FP32 (thanks to LDj3SNuD
* Float operands don't need to use the same register when VEX is supported
* Add a new register allocator, higher quality code for hot code (tier up), and other tweaks
* Some nits, small improvements on the pre allocator
* CpuThreadState is gone
* Allow changing CPU emulators with a config entry
* Add runtime identifiers on the ARMeilleure project
* Allow switching between CPUs through a config entry (pt. 2)
* Change win10-x64 to win-x64 on projects
* Update the Ryujinx project to use ARMeilleure
* Ensure that the selected register is valid on the hybrid allocator
* Allow exiting on returns to 0 (should fix test regression)
* Remove register assignments for most used variables on the hybrid allocator
* Do not use fixed registers as spill temp
* Add missing namespace and remove unneeded using
* Address PR feedback
* Fix types, etc
* Enable AssumeStrictAbiCompliance by default
* Ensure that Spill and Fill don't load or store any more than necessary
2019-08-08 18:56:22 +00:00
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// Use old ChocolArm64 ARM emulator
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"enable_legacy_jit": false,
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2019-02-28 02:03:31 +00:00
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2019-04-15 23:22:55 +00:00
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// Enable or disable ignoring missing services, this may cause instability
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2019-05-02 23:29:01 +00:00
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"ignore_missing_services": false,
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2019-04-15 23:22:55 +00:00
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2019-02-11 12:00:32 +00:00
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// The primary controller's type
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// Supported Values: Handheld, ProController, NpadPair, NpadLeft, NpadRight
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"controller_type": "Handheld",
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2019-05-02 23:29:01 +00:00
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// Enable or disable "direct keyboard access (HID) support" (Provides games access to your keyboard as a text entry device).
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2019-07-22 17:15:46 +00:00
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"enable_keyboard": false,
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2019-05-02 23:29:01 +00:00
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2019-02-11 12:00:32 +00:00
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// Keyboard Controls
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// https://github.com/opentk/opentk/blob/master/src/OpenTK/Input/Key.cs
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"keyboard_controls": {
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// Left JoyCon Keyboard Bindings
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"left_joycon": {
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"stick_up": "W",
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"stick_down": "S",
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"stick_left": "A",
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"stick_right": "D",
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"stick_button": "F",
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"dpad_up": "Up",
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"dpad_down": "Down",
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"dpad_left": "Left",
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"dpad_right": "Right",
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"button_minus": "Minus",
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"button_l": "E",
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"button_zl": "Q"
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},
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// Right JoyCon Keyboard Bindings
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"right_joycon": {
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"stick_up": "I",
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"stick_down": "K",
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"stick_left": "J",
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"stick_right": "L",
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"stick_button": "H",
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"button_a": "Z",
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"button_b": "X",
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"button_x": "C",
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"button_y": "V",
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"button_plus": "Plus",
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"button_r": "U",
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"button_zr": "O"
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2019-04-22 06:54:31 +00:00
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},
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"hotkeys": {
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"toggle_vsync": "Tab"
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2019-02-11 12:00:32 +00:00
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}
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},
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// Controller Controls
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2019-08-05 18:58:27 +00:00
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"joystick_controls": {
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2019-02-11 12:00:32 +00:00
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// Whether or not to enable Controller support
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"enabled": true,
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// Controller Device Index
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"index": 0,
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// Controller Analog Stick Deadzone
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"deadzone": 0.05,
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// The value of how pressed down each trigger has to be in order to register a button press
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"trigger_threshold": 0.5,
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// Left JoyCon Controller Bindings
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"left_joycon": {
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2019-08-05 18:58:27 +00:00
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"stick": "Axis0",
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"stick_button": "Button13",
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"dpad_up": "Hat0Up",
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"dpad_down": "Hat0Down",
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"dpad_left": "Hat0Left",
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"dpad_right": "Hat0Right",
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"button_minus": "Button10",
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"button_l": "Button6",
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"button_zl": "Button8"
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2019-02-11 12:00:32 +00:00
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},
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// Right JoyCon Controller Bindings
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"right_joycon": {
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2019-08-05 18:58:27 +00:00
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"stick": "Axis2",
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"stick_button": "Button14",
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"button_a": "Button0",
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"button_b": "Button1",
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"button_x": "Button3",
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"button_y": "Button4",
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"button_plus": "Button11",
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"button_r": "Button7",
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"button_zr": "Button9"
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2019-02-11 12:00:32 +00:00
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}
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}
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}
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