forked from Mirror/Ryujinx
ec8d4f3af5
* Replace unicorn bindings with Nuget package * Use nameof for ValueSource args * Remove redundant code from test projects * Fix wrong values for EmuStart() Add notes to address this later again * Improve formatting * Fix formatting/alignment issues
153 lines
No EOL
5.2 KiB
C#
153 lines
No EOL
5.2 KiB
C#
#define SimdLogical32
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using ARMeilleure.State;
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using NUnit.Framework;
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namespace Ryujinx.Tests.Cpu
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{
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[Category("SimdLogical32")]
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public sealed class CpuTestSimdLogical32 : CpuTest32
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{
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#if SimdLogical32
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#region "ValueSource (Types)"
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private static ulong[] _8B4H2S_()
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{
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return new[] { 0x0000000000000000ul, 0x7F7F7F7F7F7F7F7Ful,
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0x8080808080808080ul, 0x7FFF7FFF7FFF7FFFul,
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0x8000800080008000ul, 0x7FFFFFFF7FFFFFFFul,
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0x8000000080000000ul, 0xFFFFFFFFFFFFFFFFul };
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}
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#endregion
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#region "ValueSource (Opcodes)"
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private static uint[] _Vbic_Vbif_Vbit_Vbsl_Vand_Vorn_Vorr_Veor_I_()
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{
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return new[]
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{
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0xf2100110u, // VBIC D0, D0, D0
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0xf3300110u, // VBIF D0, D0, D0
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0xf3200110u, // VBIT D0, D0, D0
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0xf3100110u, // VBSL D0, D0, D0
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0xf2000110u, // VAND D0, D0, D0
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0xf2300110u, // VORN D0, D0, D0
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0xf2200110u, // VORR D0, D0, D0
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0xf3000110u // VEOR D0, D0, D0
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};
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}
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private static uint[] _Vbic_Vorr_II_()
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{
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return new[]
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{
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0xf2800130u, // VBIC.I32 D0, #0 (A1)
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0xf2800930u, // VBIC.I16 D0, #0 (A2)
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0xf2800110u, // VORR.I32 D0, #0 (A1)
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0xf2800910u // VORR.I16 D0, #0 (A2)
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};
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}
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#endregion
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[Test, Pairwise]
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public void Vbic_Vbif_Vbit_Vbsl_Vand_Vorn_Vorr_Veor_I([ValueSource(nameof(_Vbic_Vbif_Vbit_Vbsl_Vand_Vorn_Vorr_Veor_I_))] uint opcode,
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[Range(0u, 5u)] uint rd,
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[Range(0u, 5u)] uint rn,
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[Range(0u, 5u)] uint rm,
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[Values(ulong.MinValue, ulong.MaxValue)] ulong z,
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[Values(ulong.MinValue, ulong.MaxValue)] ulong a,
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[Values(ulong.MinValue, ulong.MaxValue)] ulong b,
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[Values] bool q)
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{
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if (q)
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{
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opcode |= 1 << 6;
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rd >>= 1; rd <<= 1;
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rn >>= 1; rn <<= 1;
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rm >>= 1; rm <<= 1;
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}
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opcode |= ((rd & 0xf) << 12) | ((rd & 0x10) << 18);
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opcode |= ((rn & 0xf) << 16) | ((rn & 0x10) << 3);
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opcode |= ((rm & 0xf) << 0) | ((rm & 0x10) << 1);
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V128 v0 = MakeVectorE0E1(z, ~z);
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V128 v1 = MakeVectorE0E1(a, ~a);
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V128 v2 = MakeVectorE0E1(b, ~b);
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SingleOpcode(opcode, v0: v0, v1: v1, v2: v2);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise]
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public void Vbic_Vorr_II([ValueSource(nameof(_Vbic_Vorr_II_))] uint opcode,
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[Values(0u, 1u)] uint rd,
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[Values(ulong.MinValue, ulong.MaxValue)] ulong z,
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[Values(byte.MinValue, byte.MaxValue)] byte imm,
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[Values(0u, 1u, 2u, 3u)] uint cMode,
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[Values] bool q)
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{
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if ((opcode & 0x800) != 0) // cmode<3> == '1' (A2)
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{
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cMode &= 1;
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}
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if (q)
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{
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opcode |= 1 << 6;
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rd >>= 1; rd <<= 1;
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}
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opcode |= ((uint)imm & 0xf) << 0;
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opcode |= ((uint)imm & 0x70) << 12;
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opcode |= ((uint)imm & 0x80) << 17;
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opcode |= (cMode & 0x3) << 9;
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opcode |= ((rd & 0xf) << 12) | ((rd & 0x10) << 18);
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V128 v0 = MakeVectorE0E1(z, ~z);
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SingleOpcode(opcode, v0: v0);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise, Description("VTST.<dt> <Vd>, <Vn>, <Vm>")]
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public void Vtst([Range(0u, 5u)] uint rd,
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[Range(0u, 5u)] uint rn,
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[Range(0u, 5u)] uint rm,
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[ValueSource(nameof(_8B4H2S_))] ulong z,
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[ValueSource(nameof(_8B4H2S_))] ulong a,
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[ValueSource(nameof(_8B4H2S_))] ulong b,
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[Values(0u, 1u, 2u)] uint size,
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[Values] bool q)
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{
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uint opcode = 0xf2000810u; // VTST.8 D0, D0, D0
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if (q)
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{
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opcode |= 1 << 6;
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rd >>= 1; rd <<= 1;
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rn >>= 1; rn <<= 1;
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rm >>= 1; rm <<= 1;
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}
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opcode |= ((rd & 0xf) << 12) | ((rd & 0x10) << 18);
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opcode |= ((rn & 0xf) << 16) | ((rn & 0x10) << 3);
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opcode |= ((rm & 0xf) << 0) | ((rm & 0x10) << 1);
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opcode |= (size & 0x3) << 20;
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V128 v0 = MakeVectorE0E1(z, ~z);
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V128 v1 = MakeVectorE0E1(a, ~a);
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V128 v2 = MakeVectorE0E1(b, ~b);
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SingleOpcode(opcode, v0: v0, v1: v1, v2: v2);
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CompareAgainstUnicorn();
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}
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#endif
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}
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} |