forked from Mirror/Ryujinx
c26f3774bd
* Implement VMULL, VMLSL, VQRSHRN, VQRSHRUN AArch32 instructions plus other fixes * Re-align opcode table * Re-enable undefined, use subclasses to fix checks * Add test and fix VRSHR instruction * PR feedback
14 lines
409 B
C#
14 lines
409 B
C#
namespace ARMeilleure.Decoders
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{
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class OpCode32SimdRegLong : OpCode32SimdReg
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{
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public bool Polynomial { get; private set; }
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public OpCode32SimdRegLong(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
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{
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Q = false;
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RegisterSize = RegisterSize.Simd64;
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Polynomial = ((opCode >> 9) & 0x1) != 0;
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}
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}
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}
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