forked from Mirror/Ryujinx
c26f3774bd
* Implement VMULL, VMLSL, VQRSHRN, VQRSHRUN AArch32 instructions plus other fixes * Re-align opcode table * Re-enable undefined, use subclasses to fix checks * Add test and fix VRSHR instruction * PR feedback
28 lines
948 B
C#
28 lines
948 B
C#
namespace ARMeilleure.Decoders
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{
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class OpCode32SimdRegElem : OpCode32SimdReg
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{
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public OpCode32SimdRegElem(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
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{
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Q = ((opCode >> 24) & 0x1) != 0;
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F = ((opCode >> 8) & 0x1) != 0;
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Size = (opCode >> 20) & 0x3;
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RegisterSize = Q ? RegisterSize.Simd128 : RegisterSize.Simd64;
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if (Size == 1)
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{
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Vm = ((opCode >> 3) & 0x1) | ((opCode >> 4) & 0x2) | ((opCode << 2) & 0x1c);
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}
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else /* if (Size == 2) */
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{
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Vm = ((opCode >> 5) & 0x1) | ((opCode << 1) & 0x1e);
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}
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if (GetType() == typeof(OpCode32SimdRegElem) && DecoderHelper.VectorArgumentsInvalid(Q, Vd, Vn) || Size == 0 || (Size == 1 && F))
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{
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Instruction = InstDescriptor.Undefined;
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}
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}
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}
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}
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